Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

N-path filters & their flicker noise of clock generation

Status
Not open for further replies.
A

Alipoursaadaty

Member level 3
Joined
Dec 4, 2015
Messages
60
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
13,625
Hi guys.
I'm a master student. I designed a receiver using N-path filters for filtering & mixing input signals.
For driving the N-path filter switches, we need to design a clock genefration with 1/N % duty-cycle.
But in the total noise of receiver, we observe flicker noise of clock generation elements & it's significant.
How do I decrease it???
please help me.
 

flicker noise is a relatively low frequency effect that "upconverts" to the RF region. So if you can lower the flicker noise of the device itself, you will have less clock jitter. Some sort of audio frequency feedback loop to bias your oscialator transistor, keeping fets outside of their voltage range extremes, applying analog feedback either in the bias network or thru a PLL referenced to a low noise crystal oscillator, are all valid ways to try to fix it
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top