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  1. #1
    Full Member level 2
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    Cadence Virtuoso: Import a large verilog netlist to cadence schematic

    Hello all,

    I imported a verilog netlist for a layout previously designed in Encounter. When I try to open the schematic and hit check&save, I get these errors:

    Error: Net "v_CALCULATION_CNTR<7:0>" shorted to net "N5512,N5511,N5510,N5509,N5508,N5507,N5506,SYNOPSYS _UNCONNECTED__0".
    Error: (DB-270004): Illegal bus reference - Can't tap "" from net "v_CALCULATION_CNTR<7:0>".
    Error: (DB-270004): Illegal bus reference - Can't tap "" from net "v_CALCULATION_CNTR<7:0>".
    Error: (DB-270004): Illegal bus reference - Can't tap "" from net "v_CALCULATION_CNTR<7:0>".
    Error: (DB-270004): Illegal bus reference - Can't tap "" from net "v_CALCULATION_CNTR<7:0>".
    Error: (DB-270004): Illegal bus reference - Can't tap "" from net "v_CALCULATION_CNTR<7:0>".
    Error: (DB-270004): Illegal bus reference - Can't tap "" from net "v_CALCULATION_CNTR<7:0>".
    Error: (DB-270004): Illegal bus reference - Can't tap "" from net "v_CALCULATION_CNTR<7:0>".
    INFO (SCH-1172): There were 8 errors and 0 warnings found in "NangateOpenCellLibrary key_expansion_KEY_SIZE0 schematic".

    Moreover, I can see lots of unconnected wires like the attached picture

    Click image for larger version. 

Name:	cadence.PNG 
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ID:	136777

    This verilog netlist was exported from SoC Encounter from a layout with no geometry or connectivity violations.

    Any suggestions ?

    EDIT: the unconnected wires are probably due to some floating output pins of std cells that are not used in the design and I don't see errors complaining about them.
    Last edited by oAwad; 9th March 2017 at 11:05.

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  2. #2
    Advanced Member level 5
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    Re: Cadence Virtuoso: Import a large verilog netlist to cadence schematic

    I tried this once and got an unreadable pile of symbols
    connected by named nets, in such disarray that it made
    no sense at all to "eyeball" inspection.

    It's possible that the process of conversion, or some
    "oops!", laid a solder dot onto a bus segment and
    shorted it all. I recommend finding one such segment,
    probe it and inspect for this kind of "forced error".

    Useless tool, last I left it.



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