Questions about vias.

Hello guys,

I have 2 questions about viad:
1) when definding a via in 2 layers board or 4 layers board i need to define thermal relif and anti pad to the via? because i saw that the vias that allegro gives have thermal and anti pad too. and what thermal relif and anti pad means?

2) i have a problem (i think this is a problem) in my design that more than 100 vias in my design are antenna vias (i have 4 layers board). how do i solve this? and what antenna via means?

Thank you very much,

what thermal relif and anti pad means?

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I'm sure the terms are well explained in Allegro manuals, otherwise Google is your friend.

Vias are usually not defined with thermal relief, only through-plated component holes. Should be disabled.
Antipads (isolation of via drills going through but not connecting to a ground plane) must be defined according to PCB design rules. 0.25 to 0.3 mm clearance between drill and ground plane is the lower limit for recent standard PCB technologies, more if high voltage is involved.

"Antenna vias" are vias with only one connecting trace. Shouldn't happen unless they have been intentionally inserted, e.g. as test points.

I am a design engineer that works with layout people... Thermal relief pads are good for making it easier to solder parts down to thermally conductive surface (more conductive than just multi-layer softboards). Thermal reliefs are bad for high frequency RF performance unless the subject is carefully reviewed.

I agree with FvM that you need to do some reading on thermal reliefs, anti-pads & anti-pads. Also talk with your design engineer. The designer should be designating where and if you need any of these features.

As mentioned, "antenna vias" only have 1 connection - they could be a test point, or perhaps more likely in your case, they are indicating you have routing/net conenction problems in your PCB layout.

Thermal reliefs can be critical to good solderability/manufacturing, but the application /use of the PCB and the size of the vias must be considered. Generally direct connects are best for RF connections and for EMI containment (stapling poured regions/board edges together), or if intentionally directing heat away from pads or dealing with constrained routing spaces like BGAs. But, that doesn't mean that thermal relief vias should never be used - they are critical with larger components and large ground or VCC plane connections to ensure good solderability on the component/pad/through hole.

I must confess I have never seen thermal relief for vias in third party designs, and never used it.

PCB can be expected to be heated uniformly in its entirety with industrial reflow processes, vias shouldn't affect solderability. There might be problems in rework if you don't provide PCB preheating. If at all, this might a criterion for prototype designs, but not for production boards.

You are assuming that production boards all go through SMT reflow or traditional wave soldering with all parts on board - there are also production boards with hand soldered parts which cannot go through these processes, and which are sold in many thousands per year. As with anything, the application, design, and processes all matter as to PCB layout choices.

Yes boards have wave soldered or hand soldered parts. But they are usually not mounted in a way that vias are affecting the solderability. It's of course different for through plated component holes, as mentioned in post #2.

I see there can be cases with vias near to wave or hand soldered component pads, but that's rather unusual, I think.

On the other hand, you sometimes need to override thermal relief rules for through plated component holes, although it affects solderability, e.g. to serve priority RF or current rating rules.

You don't need or want thermal relief on a via.
IPC rules on thermal relief is each spoke should be equal to the trace width required to carry the current divided by the number of spokes...
Hand soldering is not the norm for production runs, selective soldering is used extensively these days...

All my connecrions are good and all is connected but im still have 106 antenna vias. the antenna vias appears when i am connecting traces from the mid layers (4 layers board) to the via, i dont know why.

Go into your project/PCBDoc properties and check the connection rules for your inner layers (or your inner layers aren't assigned to the nets).
What CAD tool are you using - I am assuming Altium Designer?

Allegro Design XL

the antenna vias appears when i am connecting traces from the mid layers (4 layers board) to the via, i dont know why.

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What's the second connection to the via? Can you see that it's actually connected?

Yes i can see, and the allegro says that all the nets and connections are connected (unrouted connections=0)

I am assuming that those vias were either placed by hand while not using the routing tool, or are left overs from an import from another CAD tool and the net connection on an inner plane net is gone.
I've had to deal with this when importing/translating ancient designs into OrCAD/Allegro. It is tedious to edit the via properties and change it for each one.
If this is your problem, I can recommend some free utilities from our Swiss friends at FlowCAD. I have used these tcl tools/extensions quite often when dealing with imported designs.
My favorite one is the "Assign Net to Via" one - it can save alot of time and allows me to just click on vias and change their netconnectivity (or fix it) when the via has been bumped and lost its net association.
Why this is not a standard tool within Allegro, I don't know.
You can access the free FlowCAD items from this link - they offer it freely for general use.
https://www.flowcad.ch/en/products/floware/free-apps