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  1. #1
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    Is everything okay with my synthesis report

    Hello,

    I ran synthesis on a IP many times with a variation in the frequency each time. and no additional constraints given during synthesis to the design.

    please look into the attachment , i observed a consistent zero slack from 500 Mhz to 1 Ghz. Is everything ok or iam missing anything ? give some suggestions

    Click image for larger version. 

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ID:	136548

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  2. #2
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    Re: Is everything okay with my synthesis report

    Quote Originally Posted by hcu View Post
    Hello,

    I ran synthesis on a IP many times with a variation in the frequency each time. and no additional constraints given during synthesis to the design.

    please look into the attachment , i observed a consistent zero slack from 500 Mhz to 1 Ghz. Is everything ok or iam missing anything ? give some suggestions

    Click image for larger version. 

Name:	Screenshot-1.png 
Views:	7 
Size:	12.6 KB 
ID:	136548
    It is possible everything is ok. You can check the design area, it should be increasing as more and more buffers and large cells are put in your design.



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  3. #3
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    Re: Is everything okay with my synthesis report

    yes , area is increased from 318k um2(@100 Mhz) to 324k um2(@1G). so, any thumb rule to say the maximum frequency for this design.
    what i am thinking is, at 100 Mhz i.e 10000ps i got a slack of 7000 ps. so 10000 - 7000 = 3000 ps which is around ~ 300 Mhz.
    so if i keep my f =300 mhz i should get a 0 slack for sure approx. but as per sheet , it is going upto 1 G.



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  4. #4
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    Re: Is everything okay with my synthesis report

    Quote Originally Posted by hcu View Post
    yes , area is increased from 318k um2(@100 Mhz) to 324k um2(@1G). so, any thumb rule to say the maximum frequency for this design.
    what i am thinking is, at 100 Mhz i.e 10000ps i got a slack of 7000 ps. so 10000 - 7000 = 3000 ps which is around ~ 300 Mhz.
    so if i keep my f =300 mhz i should get a 0 slack for sure approx. but as per sheet , it is going upto 1 G.
    it is not that simple. the synthesis tool will use more and more advanced tricks once you start to request challenging constraints.

    one way to find the maximum, or very close to maximum, is to largely overconstrain the design.



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