hetirajhimanshu
Newbie level 6
Difference between n well drawing and n well pin layers in cadence virtuoso layoutXL
I am drawing a layout of an inverter in cadence virtuoso layout XL. The problem is there are two layers visible in P MOS one is n well draw and other one is n well pin. and by default it (n well pin) is showing connection to VDD. As a result of this when I tried to connect the out, it is showing short circuit with vdd. I dont know how to solve this issue ? Please someone xplain me as soon as possible .
I am drawing a layout of an inverter in cadence virtuoso layout XL. The problem is there are two layers visible in P MOS one is n well draw and other one is n well pin. and by default it (n well pin) is showing connection to VDD. As a result of this when I tried to connect the out, it is showing short circuit with vdd. I dont know how to solve this issue ? Please someone xplain me as soon as possible .