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Need Some advice to write verilog code for CAM memory

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Adnan86

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Hi, I want to write verilog code for CAM memory. For RAM memory it was easy, just need define ram and i = i+1 in loop to access all address and content. But here i should match data input with data memory,
but I cant find optimize solution to search content at first and then find address.
I mean below code, but this one its not optimize and i dont like to use for loop.
Code: 
for (i =0; i < DEPTH; i+1)
if (data_IN == ram[i]) then
valid = 1; // data input match with data in memory
address = i;
else 
valid = 0;
for example data input its 8 bits and depth = 100;
I will appreciate for any advice.
Thanks for your consideration.
 

Adnan86 said:
Hi, I want to write verilog code for CAM memory. For RAM memory it was easy, just need define ram and i = i+1 in loop to access all address and content. But here i should match data input with data memory,
but I cant find optimize solution to search content at first and then find address.
I mean below code, but this one its not optimize and i dont like to use for loop.
Code: 
for (i =0; i < DEPTH; i+1)
if (data_IN == ram[i]) then
valid = 1; // data input match with data in memory
address = i;
else 
valid = 0;
for example data input its 8 bits and depth = 100;
I will appreciate for any advice.
Thanks for your consideration.
Click to expand...


CAMs usually don't work like that. it seems you are trying to use a RAM that emulates a CAM behaviour. when using a true CAM, you query it once, and the query goes to every single 'address'. you don't need to loop through.
 

How I can query once ?
because in one single clk, I just can compare input with one data in memory. however i have a lot of data in memory.
 

Adnan86 said:
How I can query once ?
because in one single clk, I just can compare input with one data in memory. however i have a lot of data in memory.
Click to expand...

you describing a traditional RAM, not a CAM.
 
Your example seems to imply that for each data word, there's either zero or one matching address.
That's a trivial CAM case, you can implement it using a regular RAM and interchange data and addresses.

A useful CAM has zero to many matching addresses for a specific content. It can't be implemented with regular RAM and single clock cycle access.
 
ThisIsNotSam said:
you describing a traditional RAM, not a CAM.
Click to expand...

The problem is that CAMs do not exist in FPGA, so they have to be emulated.

To the OP: your code will not work for an FPGA because it uses a for loop, as if it is a software program. For an FPGA, you need to loop through the addresses using a counter, not a for loop. Or you could try just swapping the address and data lines.
 
tanks for your advice.for first of my work, i try this cod. its not complete. I put 100 number in memory.
Code: 
always @ (posedge clk)
		
		if (rst || (addra > DEPTH))
			begin
			addra <= 0;
			valid <= 0;
			valid_address <= 0;
			valid_data    <= 0;
			search_finish <= 0;
			end
		else if (search_data == temp_data)
		begin
			valid <= 1;
			valid_address <= addra;
			valid_data    <= search_data;
			search_finish <= 1;
		end
		else if ((search_data != temp_data) && (addra < DEPTH))
		begin
			valid <= 0;
			valid_address <= 0;
			valid_data    <= 0;
			search_finish <= 0;
			addra <= addra + 1;
		end
		else
		begin
			valid <= 0;
			valid_address <= 0;
			valid_data    <= 0;
			search_finish <= 1;
			addra <= 0;
		end
Are this code be simple CAM ?
 

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