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BJTs not getting into saturation in opamp!

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fateme m

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BJT.png

I am trying to simulate an opamp for a Band Gap Reference, all the mosfets are in saturation but not the BJTs... can't figure out why... and I only have this npn available in my tsmc18rf library. I am applying 1v as the power supply in vdd and applying 0.6 dc volts to in+ and in- .

and another question is does the opamp and the BGR itself have to have the same power supply level? or could the BGR, for example work with 2.7 volts while the opamp works with 1 volt supply? I'm an amature:sad:
 

fateme m said:
and another question is does the opamp and the BGR itself have to have the same power supply level? or could the BGR, for example work with 2.7 volts while the opamp works with 1 volt supply? I'm an amature:sad:
Click to expand...

It looks as though the righthand section can have a different positive supply from the lefthand section. Signals from the lefthand go to bias N-devices at the righthand, and the current has a path to a common ground rail.
 

You know that saturated mode of BJT involves forward biased BC junction with low current gain? It's not the active mode as for MOSFET.

The circuit can work as an operational amplifier only for a very restricted common mode range, hard to decide if this is possible without seeing the connected circuit. I guess, it doesn't work.
 

Thanks for the reply,
How can I know what restricted common mode range is? so for my amplifier the BJTs better to be in active region and not saturation? for mosfets:
region 1 ---> triode
region 2 ---> sat
what number represents the active region for BJTs ?
 

Yes, "saturation" means almost the opposite for
MOS than for BJTs. The BJT analogue would be
"forward active" region. Don't know what the
simulator OP "region" would display, but for a
BJT "saturation" is where you surely do not want
to be for a linear circuit.
 

fateme m said:
How can I know what restricted common mode range is?

so for my amplifier the BJTs better to be in active region and not saturation?

what number represents the active region for BJTs ?
Click to expand...

The simulator will show you, surely, by just cycling through 0 to 1V inputs in 50mV to 100mV steps? Maybe it'll do an input/output range of ~350mV to ~950mV...

Active region is the output slope that reflects the change in input, saturation is the straight, (almost) horizontal line at the top of the curve/slope.

The NPNs will do something useful from ???mV, maybe 200 - 350mV upwards, until that model you're using saturates, so maybe up to ~1V, if that's the supply voltage.

r.e. BJT differential pair - you can extend the ("useful") input range by adding a resistor between the PMOS active load and the BJT collector, and emitter degeneration resistors make response more linear (but lower the gain).
 
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The BJT Q3 and Q4 don't actually form a differential pair, they are missing a common emitter current source or resistor. Of course the low 1V power supply leaves little room, but 100 or 200 mV common mode range should be possible though.

Without seeing the overall circuit, I really don't know if this is a useful amplifier design or an error of thinking.
 
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    d123

    d123

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BGR.png
The overall circuit is not working it has a PSRR of 8dB , but it must be designed for -70dB PSRR. and the amplifier I used works with 1 volt but I have used it in this bandgap reference which works with 2.7 volts (do both the amp and the BGR need to work with 2.7 volts? ), the bandwidth of the amplifier is about 800Khz, How can I increase it to be about 1 Mhz?
 

Looks to me like you need a better startup circuit, the
reference elements are not "lit up" to where the bandgap
PTAT current locks in. The core amplifier circuit shown
in the first post, looks like it will not work well for any
but perhaps one nominal PVT point (if that). Many CMOS
op amp designs are out there in the public literature,
I suggest you not invent another unless this is your
tasking.

"Works at 1V" might be very specifically true for some
aspect(s) but I doubt that "amp" is general-purpose
or robust enough to survive the design process as-is.
 

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