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    can we connect axi gpio signals to the axi traf gen start stop bits?

    1) can we connect axi gpio signals which is on the slave side to the axi traffic gen start, stop bits, which is on the master side of the axi interconnect, how can we do it??, since my axi gpios width cannot be a single bit which can be given to the axi traffic gen start stop bits.

    2)I want to enable my axi traffic gen, on start bit from the axi gpio and write the data into the axi register which is on the slave side??

    kindly help me I'm beginner to vivado model based design, i have build design as per the image attached.

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    Re: can we connect axi gpio signals to the axi traf gen start stop bits?

    There isn't any reason that it can't be connected, I think you'll have to separate it out so it's not an external GPIO as show currently. I'm not sure if you can mix pins as external and internal on a single GPIO.

    It might be easier to add another GPIO that controls the start and stop pins only and doesn't connect externally.


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    Re: can we connect axi gpio signals to the axi traf gen start stop bits?

    Thanks for the reply, yes i was able to connect it by expanding the gpio pins and connecting it to start stop, i have tested the transaction from axi traffic gen to bram by exporting the design to SDK, I want to test the function of axi gpio, that gpio is not dedicated external pins, and how do we enable axi gpio to logic "1" and logic "0" when ever i wish to when it is connected to axi traffic generator??



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    Re: can we connect axi gpio signals to the axi traf gen start stop bits?

    Quote Originally Posted by beginner_0029 View Post
    Thanks for the reply, yes i was able to connect it by expanding the gpio pins and connecting it to start stop, i have tested the transaction from axi traffic gen to bram by exporting the design to SDK, I want to test the function of axi gpio, that gpio is not dedicated external pins, and how do we enable axi gpio to logic "1" and logic "0" when ever i wish to when it is connected to axi traffic generator??
    I though you already had that figured out. You can't control it from the AXI traffic generator as that will be stopped if the stop is sent and can never be re-enabled. Isn't the ZYNQ processing subsystem going to enable/disable the axi traffic generator? The AXI interconnect block will arbitrate between the two masters.


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    Re: can we connect axi gpio signals to the axi traf gen start stop bits?

    i have used vio (virtual start and stop bits) to control start and stop bits of traffic generator, hence we can make stop bit zero and start bit one again and make the transaction whenever i wish to, but i am not getting the data generated in sequential order and it is generating random data numbers, can we have a seqential data like counter generating from the axi traffic gen?



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    Re: can we connect axi gpio signals to the axi traf gen start stop bits?

    Have you read the documentation on the core? Seems like you haven't. The documentation seems to indicate that you can by modifying the memory initialization files that control the traffic patterns.

    Initialization support through Memory
    initialization files to internal RAM
    (CMDRAM, PARAMRAM, and MSTRAM)
    allows you to initialize the contents of all
    RAMs for a desired traffic profile.
    But I'm not going to spend my time reading the entire document to determine how to do this for you.


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    Re: can we connect axi gpio signals to the axi traf gen start stop bits?

    hey anyways thanks for your time i should read it .



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