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Trying to export a sub-circuit in verilog from a structural gate netlist in verilog

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arunkumarv

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Hi All,

I have a structural gate-level verilog netlist of a fairly large circuit composed of more than 50K logic gates and 4K flipflops.
I would like to extract part of this circuit and export it as another verilog netlist. Please note that the netlist I am dealing with
is a flattened one having no sub-circuits in it.

More specifically, I need to eliminate some gates and flip-flops from the original netlist and their associated paths and save the
remaining circuit as a new netlist. I have found that a tool called NETEDIT is capable of doing it. Unfortunately, this tool is no more
supported. It would be great if I can get some pointers to a new tool.

Thanks,
Arun
 

What does this have to do with FPGAs? Perhaps you meant to post this in the ASIC section?
 

arunkumarv said:
Hi All,

I have a structural gate-level verilog netlist of a fairly large circuit composed of more than 50K logic gates and 4K flipflops.
I would like to extract part of this circuit and export it as another verilog netlist. Please note that the netlist I am dealing with
is a flattened one having no sub-circuits in it.

More specifically, I need to eliminate some gates and flip-flops from the original netlist and their associated paths and save the
remaining circuit as a new netlist. I have found that a tool called NETEDIT is capable of doing it. Unfortunately, this tool is no more
supported. It would be great if I can get some pointers to a new tool.

Thanks,
Arun
Click to expand...

a text editor with the search and replace function can do what you need.
 

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