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Describing a state machine in requirements

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Has anyone come up with a good way of describing a state machine in requirements without access to the state signals, e.g. so it is directly testable?

For instance

1) The state machine shall change state from state A to state B when Z = 1.

2) When in state B, output C shall be set to 1

When writing a test for these requirements you would have a test procedure like:

1) Reset
2) Set Z = 0
3) Check C is 0
4) Set Z = 1
5) Check C is 1

This only implies that you are in state B, but does not directly test it, as C=1 could also be set in some other state (not described above). Is there a better way of writing the requirements so that you can test them without giving the test module access to the state machine state signals?
 

If you have no internal visibility, then you can only hope to test the output for compliance. This would be Black box testing.

How are you writing these tests? have you considered SVA?
 

Because I also need to run gate level simulations. I have used Modelsim signal spy to view internal signals for testing. You can find the same signal in the netlist so can still do this but I would rather avoid it.

- - - Updated - - -

I need to do post layout simulations so not sure assertions are viable. I have no experience of SystemVerilog however, it is not widely used (yet!) in Aerospace as far as I know. I have used Modelsim signal spy function to view internal signals and you can find the equivalent signals in the netlist but this is messy and I would prefer a more elegant solution. Bringing out the state signals to external pins via a multiplexer or serial link or something is OK but I wondered if anyone had a better solution.
 

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