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please help in testbench in vhdl

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maryam2015

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Code VHDL - [expand]
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
 
use std.textio.all;  
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY fft_test IS
END fft_test;
 
ARCHITECTURE behavior OF fft_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT fft1
    PORT(
         clk : IN  std_logic;
         nfft : IN  std_logic_vector(4 downto 0);
         nfft_we : IN  std_logic;
         start : IN  std_logic;
         xn_re : IN  std_logic_vector(7 downto 0);
         xn_im : IN  std_logic_vector(7 downto 0);
         fwd_inv : IN  std_logic;
         fwd_inv_we : IN  std_logic;
         rfd : OUT  std_logic;
         xn_index : OUT  std_logic_vector(9 downto 0);
         busy : OUT  std_logic;
         edone : OUT  std_logic;
         done : OUT  std_logic;
         dv : OUT  std_logic;
         xk_index : OUT  std_logic_vector(9 downto 0);
         xk_re : OUT  std_logic_vector(7 downto 0);
         xk_im : OUT  std_logic_vector(7 downto 0);
         blk_exp : OUT  std_logic_vector(4 downto 0)
        );
    END COMPONENT;
   --Inputs
   signal clk : std_logic := '0';
   signal nfft : std_logic_vector(4 downto 0) := (others => '0');
   signal nfft_we : std_logic := '0';
   signal start : std_logic := '0';
   signal xn_re : std_logic_vector(7 downto 0) := (others => '0');
   signal xn_im : std_logic_vector(7 downto 0) := (others => '0');
   signal fwd_inv : std_logic := '0';
   signal fwd_inv_we : std_logic := '0';
 
    --Outputs
   signal rfd : std_logic;
   signal xn_index : std_logic_vector(9 downto 0);
   signal busy : std_logic;
   signal edone : std_logic;
   signal done : std_logic;
   signal dv : std_logic;
   signal xk_index : std_logic_vector(9 downto 0);
   signal xk_re : std_logic_vector(7 downto 0);
   signal xk_im : std_logic_vector(7 downto 0);
   signal blk_exp : std_logic_vector(4 downto 0);
 
   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: fft1 PORT MAP (
          clk => clk,
          nfft => nfft,
          nfft_we => nfft_we,
          start => start,
          xn_re => xn_re,
          xn_im => xn_im,
          fwd_inv => fwd_inv,
          fwd_inv_we => fwd_inv_we,
          rfd => rfd,
          xn_index => xn_index,
          busy => busy,
          edone => edone,
          done => done,
          dv => dv,
          xk_index => xk_index,
          xk_re => xk_re,
          xk_im => xk_im,
          blk_exp => blk_exp
        );
        clk<= not clk after 50ns;  
    process(clk)
     file f : text;
     constant filename : string :="input.txt";
     variable L : string;
     variable i : integer:=0;
     variable b : std_logic_vector(7 downto 0);
     begin
     file_open(input,read_mode);
     if((i<=256) and (not endfile(f))) then
     readline(f,l);
     read (f,l,conv_integer(b));
     xn_re<=b;
     i:=i+1;
     end if;
    end process;
     nfft<="00110";
     nfft_we<='1';
     start<='1';
     fwd_inv<='1';
     fwd_inv_we<='1';
END;



i want to calculate fft in vhdl and write above testbench but this error occur
Line 124: Expecting type line for <l>.
Line 122: Expecting type string for <read_mode>.ERROR:HDLCompiler:432 -
Line 125: Formal <arg> has no actual or default value.
Line 125: Type integer is not an array type and cannot be indexed.
Line 40: Unit <behavior> ignored due to previous errors.


can anyone help me?
 
Last edited by a moderator:

Doesn't help that your line numbers don't appear to tie up...

Do you really want to read a line from the file every clock cycle?

I haven't been over file i.o for quite some time but there looks some errors there, for one the "filename" constant doesn't appear to be used anywhere......
 

Upto Line nos 108 is visible.

There are numerous eg of VHDL file read floating around. Study one of them and compare it with your code.


begin
.
.
process
file file_pointer : text;
.
.
begin
.
.
--Open the file write.txt from the specified location for writing(WRITE_MODE).
file_open(file_pointer,"C:\write.txt",WRITE_MODE);
.
.

btw- I see that you found the TB for a 256 ppt FFT before the actual FFR core (https://www.edaboard.com/threads/363424/) ;-)
 
Last edited:


Code VHDL - [expand]
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--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   01:19:56 01/20/2017
-- Design Name:   
-- Module Name:   F:/Users/fft/fft_test.vhd
-- Project Name:  fft
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: fft1
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use std.textio.all;  
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY fft_test IS
END fft_test;
 
ARCHITECTURE behavior OF fft_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT fft1
    PORT(
         clk : IN  std_logic;
         nfft : IN  std_logic_vector(4 downto 0);
         nfft_we : IN  std_logic;
         start : IN  std_logic;
         xn_re : IN  std_logic_vector(7 downto 0);
         xn_im : IN  std_logic_vector(7 downto 0);
         fwd_inv : IN  std_logic;
         fwd_inv_we : IN  std_logic;
         rfd : OUT  std_logic;
         xn_index : OUT  std_logic_vector(9 downto 0);
         busy : OUT  std_logic;
         edone : OUT  std_logic;
         done : OUT  std_logic;
         dv : OUT  std_logic;
         xk_index : OUT  std_logic_vector(9 downto 0);
         xk_re : OUT  std_logic_vector(7 downto 0);
         xk_im : OUT  std_logic_vector(7 downto 0);
         blk_exp : OUT  std_logic_vector(4 downto 0)
        );
    END COMPONENT;
   --Inputs
   signal clk : std_logic := '0';
   signal nfft : std_logic_vector(4 downto 0) := (others => '0');
   signal nfft_we : std_logic := '0';
   signal start : std_logic := '0';
   signal xn_re : std_logic_vector(7 downto 0) := (others => '0');
   signal xn_im : std_logic_vector(7 downto 0) := (others => '0');
   signal fwd_inv : std_logic := '0';
   signal fwd_inv_we : std_logic := '0';
 
    --Outputs
   signal rfd : std_logic;
   signal xn_index : std_logic_vector(9 downto 0);
   signal busy : std_logic;
   signal edone : std_logic;
   signal done : std_logic;
   signal dv : std_logic;
   signal xk_index : std_logic_vector(9 downto 0);
   signal xk_re : std_logic_vector(7 downto 0);
   signal xk_im : std_logic_vector(7 downto 0);
   signal blk_exp : std_logic_vector(4 downto 0);
 
   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: fft1 PORT MAP (
          clk => clk,
          nfft => nfft,
          nfft_we => nfft_we,
          start => start,
          xn_re => xn_re,
          xn_im => xn_im,
          fwd_inv => fwd_inv,
          fwd_inv_we => fwd_inv_we,
          rfd => rfd,
          xn_index => xn_index,
          busy => busy,
          edone => edone,
          done => done,
          dv => dv,
          xk_index => xk_index,
          xk_re => xk_re,
          xk_im => xk_im,
          blk_exp => blk_exp
        );
        clk<= not clk after 50ns;  
    process(clk)
     file f : text;
     constant filename : string :="output.txt";
     variable L : integer;
     variable i : integer:=0;
     begin
     file_open(output,read_mode);
     if((i<=256) and (not endfile(f))) then
     xn_re<=readline(f,l);
     i:=i+1;
     end if;
    end process;
     nfft<="00110";
     nfft_we<='1';
     start<='1';
     fwd_inv<='1';
     fwd_inv_we<='1';
END;

 
Last edited by a moderator:

i want to calculate fft in vhdl and write above testbench but this error occur
Line 124: Expecting type line for <l>.
Line 122: Expecting type string for <read_mode>.ERROR:HDLCompiler:432 -
Line 125: Formal <arg> has no actual or default value.
Line 125: Type integer is not an array type and cannot be indexed.
Line 40: Unit <behavior> ignored due to previous errors.

What is with the quality of questions posted on edaboard!? Gee I think I'll post code that is no longer aligned with my errors, now I'll post the code again and have the alignment changed even more so none of the line number match!

based on the above line numbering using the original code and lining up line 40 with the architecture statement:

Line 122: file_open(input,read_mode);
Line 124: readline(f,l);
Line 125: read (f,l,conv_integer(b));

Basically this looks wrong as you've got the wrong types on some of those variables, but I'm not used to writing VHDL textio stuff, so I might be mistaken (though I'm probably right as you've got errors).

You sure use terrible names for your signals, single characters signal names? So once you run out of the alphabet...what next two character names?
 

you cannot open OUTPUT in read mode, as it is an implicitly declared file for reading/writing to the output console.
L needs to be type line, not integer.
Did you really want to read a value in on every rising and falling edge of the clock?
 

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