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9 words of question --> 9 words of answer.
If you need a more detailed answer you first need to give a more detailed description.
My recommendation:
* first read about ethernet protocol
* then read about ethernet PHY (verilog if you need)
* then try to find a solution on your own
* show us your solution
* ask dedicated questions
Write your own logic such that you can read out the 1st 12 bytes of the complete frame from the receive-FIFO (assuming a FIFO is present after the MAC core). Thats your DA and SA.
As to the Verilog code, I am pretty sure no-body will just give it out to you. Write your own logic and do it yourself. You may ask questions here if you have problems.
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