sps101
Newbie level 6
I am designing a chain of transmission gates in 65nm but having a problem with the calibre view generation. For a single transmission gate, the DRC, LVS and PEX works perfectly and I am able to extract the calibre view. Now, when I make the top level block consisting of a bunch of transmission gates, the DRC and LVS is clean, the PEX is also clean, however, the calibre view extraction fails.
The cellmap includes the connectivity for the required transistors.
What could be the problem ?
The cellmap includes the connectivity for the required transistors.
What could be the problem ?