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A very good book for your reference
Writing Testbenches: Functional Verification of HDL Models, Second Edition
by Janick Bergeron https://www.amazon.com/exec/obidos
Here is first edition for your reference **broken link removed**
IC tester apply test patterns in cycle base. There are several process to wirte test patterns for the tester to test the chip:
- ATPG (the test patterns are automatically generated by aptg tool)
- Dump files (VCD/EVCD) from functional simulation, required some tools to convert the files to tester format.
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