Dragon65
Newbie level 6
Good afternoon!
I have elaborated topology for my LNA antenna amplifier, and after that i tried simulate my amplifier with topology in schemanic. And DC results for biasing transistors too much differ from those without topologie. What can cause difference?
Could you also give me a link for use Ads Momentum and EM simulation?
I have removed all breaks in topology. Now i guess it can be in VIA elements(that is holes for connecting to ground)
The vias is cond layer(as the top layer), is it wrong? Layer for ground is cond2.
I have elaborated topology for my LNA antenna amplifier, and after that i tried simulate my amplifier with topology in schemanic. And DC results for biasing transistors too much differ from those without topologie. What can cause difference?
Could you also give me a link for use Ads Momentum and EM simulation?
I have removed all breaks in topology. Now i guess it can be in VIA elements(that is holes for connecting to ground)
The vias is cond layer(as the top layer), is it wrong? Layer for ground is cond2.