Is it possible to debug DDR memory using ILA core?? (Xilinx board)

Hi.

I have a problem with the use of ILA core.

I am attempting to debug a system configured with 'PCIe-AXI-MIG' using ILA core.

At this time, AXI can be debugged with ILA core, but DDR memory cannot be debugged. Especially, I want to see the address of DDR memory. (c0_ddr4_adr signal)

When I opened 'Synthesized Design', Vivado show this message "[Chipscope 16-3] Cannot debug net 'design_1_i/ddr4_0_C0_DDR4_ADR[0]'; it is not accessible from the fabric routing." Other port are same.

Is it impossible to see the address of DDR memory using ILA core?

Please answer.

What do you mean by "see the address of DDR memory"?

You write to a known location of the DDR3 using the MIG interface and then read back from the same address. If if get back the data you have written, your design is functioning.

Are you using a MIG with AXI interface? Well then the AXI response channels (B*/R*) will also indicate if handshaking was successfully achieved or not. The 2 bit error response signal is a good indicator for the AXI interconnect.

These are the easier ways to check if the DDR is functioning properly.

dpaul said:

What do you mean by "see the address of DDR memory"?

You write to a known location of the DDR3 using the MIG interface and then read back from the same address. If if get back the data you have written, your design is functioning.

Are you using a MIG with AXI interface? Well then the AXI response channels (B*/R*) will also indicate if handshaking was successfully achieved or not. The 2 bit error response signal is a good indicator for the AXI interconnect.

These are the easier ways to check if the DDR is functioning properly.

Click to expand...

I use Xilinx MET driver (xapp1022).

Using that driver, I wrote data from PC -> PCIe -> AXI -> MIG.

I can debug from PCIe to AXI, from AXI to MIG.

I want to see the after MIG.

I want to see the after MIG.

Click to expand...

The quoted message seems to suggest that it's not possible. Only design nodes with connectivity to logic fabric can be tapped.

It should be possible to debug the design in post synthesis simulation.

FvM said:

The quoted message seems to suggest that it's not possible. Only design nodes with connectivity to logic fabric can be tapped.

It should be possible to debug the design in post synthesis simulation.

Click to expand...

If I add buffer or register after ddr4 ram, can I debug between ddr4 ram and buffer (or register)?

Need to look at the FPGA hardware features to see if the address output can be accessed somehow. Adding buffers will most likely ruin the timing.

If I add buffer or register after ddr4 ram, can I debug between ddr4 ram and buffer (or register)?

Click to expand...

Due to the volume of data there are generally FIFOs before/after DDR3/4 (Xilinx has something called virtual FIFO).
If that FIFO/memory lies within the addressable range of your system bus, in principle, yes one can see the data.

I still don't understand the efficacy of you posts #1 and #3.

dpaul said:

Due to the volume of data there are generally FIFOs before/after DDR3/4 (Xilinx has something called virtual FIFO).
If that FIFO/memory lies within the addressable range of your system bus, in principle, yes one can see the data.

I still don't understand the efficacy of you posts #1 and #3.

Click to expand...

I want to check the address transition between AXI and DDR4 memory.