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Bosechandran

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verilog delay problem

Dear sir,
how to increase or decrease delay between two pulses on a same signal. i want after every two pulse need some delay. expecting verilog code. i tried verilog code both u down clock pulse width vary or getting delayed out. i dont want that

thank you
 

Re: verilog delay problem

Hi,

expecting verilog code.
Click to expand...
--> don't expect anyone doing your job.

You need to specify "delay". It could be in ps, ns ... up to hours or more

Usually you have a high frequency system clock, and you delay the signsl in multiples of clock_period_time. Maybe by using a shift register.

For longer delay times you may consider to include RAM.

If you need a delay less than one clock_period_time then consider to add gates (buffers) in the signal line.

Klaus
 

Re: verilog delay problem

In the post https://www.edaboard.com/threads/362344/ at #3 I already pointed out to you how this forum works.

See my reply @ #6 and subsequent replies in the post https://www.edaboard.com/threads/361519/ to get an idea how to insert delays between two clocked pulses. Use counters for achieving delays between the pulses.

Again - Show us what you have done and understood.
 

Re: verilog delay problem

Bosechandran said:
Dear sir,
how to increase or decrease delay between two pulses on a same signal. i want after every two pulse need some delay. expecting verilog code. i tried verilog code both u down clock pulse width vary or getting delayed out. i dont want that

thank you
Click to expand...

hi,

what is your clock frequency?
how much delay you want in your signal, (can you show a digram) ?

the delay must be constant through out the signal or it will vary?

i tried verilog code both u down clock pulse width vary or getting delayed out
Click to expand...

if you post your code, its better, you will get more help for correcting the code. from your above statement its not clear what type of signal you want :(

regards
 

Re: verilog delay problem

no need to do my job. its a 0.01% in my work. just asked a friendly manner. u r not eligible to criticize me. sorry others
 

Re: verilog delay problem

Bosechandran said:
no need to do my job. its a 0.01% in my work. just asked a friendly manner. u r not eligible to criticize me. sorry others
Click to expand...

Anything you post can be criticized by anyone for whatever reason (right or wrong). The fact is you've made posts that want others to do your work for you. This forum is not a free consulting service.

If this is truly 0.01% of your work then give this to someone else who is capable of doing the work without having to get on edaboard to do their job. Hmm, just occurred to me, perhaps you are really saying you don't need to do your own work (as you get others to do it for you, i.e. edaboard) and you only do 0.01% of your actual work. :wink::laugh:
 

Re: verilog delay problem

This is a free consulting service. It just doesn't have any accuracy, timeliness, or reliability guarantees.

I suspect the top posters have never started threads, but it actually is free.

However, if you have a thread that isn't a question it will be moderated. This is clearly stack-overflow after all.

(4 reelz -- y u no kno dis frm de "no ebooks" ner "System C LRM" stkys?)
 

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