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Hierarchically forcing VHDL signals during simulation

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shaiko

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Hello,

I have a VHDL testbench entity named "tb_top"
Inside this entity, I instantiate a component named "top"
Inside "top" I have a signal:
Code: 
signal clock : std_logic ;

In the synthesized design, "clock" is connected to an output of a PLL.
In simulation however, I want to speed things up and avoid using the PLL model.
Therefore, I want to FORCE "clock" from "tb_top".

I know that VHDL 2008 has a mechanism that allows hierarchical signal assignments.
Something like:
Code: 
<< signal tb_top.top.clock : std_logic >> <= some_value ;

What is the correct syntax for it ?
 

Why are you FORCE ing something? that will override whats there. Easier just to replace the PLL with a model that generates a clock, or connect the clock at the top level to something?

In terms of heirarchical names - the syntax looks correct. Usually it's easier to alias the signal locally so you have a nice name rather than the cumbersome external name every time you want to use it.

There are plenty of syntax guides out there -try google:
https://www.synthworks.com/papers/vhdl_2008_DASC_s.pdf
 

Why are you FORCE ing something? that will override whats there.
Click to expand...
Yes, I know. It's just the PLL's output - there's no problem forcing it with a simulated clock.
Easier just to replace the PLL with a model that generates a clock, or connect the clock at the top level to something?
Click to expand...
That's how I do it now. Just wanted to do it externally using VHDL 2008...

The syntax I used doesn't work...

There are plenty of syntax guides out there -try google:
https://www.synthworks.com/papers/vhdl_2008_DASC_s.pdf
Click to expand...
As always, I did. And came across this same document...

In page 9, there're 2 examples:
Code: 
A <= <<signal [COLOR="#FF0000"].[/COLOR]top_ent.u_comp1.my_sig : std_logic_vector >>;
Code: 
Alias u1_my_sig is <<signal u1.my_sig : std_logic_vector >>;

In the first example, what is the purpose of the "dot" left to the word "top" (marked in red) ?
Why does the second example lack a dot left of "u1" ?
 

I just love how the synthworks paper above highlights the VHDL2008 additions and looking at it (I've mostly coded in VHDL '87 and '93) I noticed nearly all of the highlighted additions are pretty much copying the stuff that was already in Verilog 2001.

I'm pretty sure the dot behaves similar to the typical directory structure meaning i.e '.' means it starts from the current hierarchical location. It sort of copies what is done in Verilog with the exception of the ^ meaning go up in hierarchy (not sure why you would use that...turns you testbench into a spaghetti (code) testbench :thumbsdown: ).


putting it in an alias shouldn't change how it's written.
 
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    shaiko

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Thanks.
Suppose I want to assign a default '0' value to the "to be forced" signal.
Alias u1_my_sig is <<signal u1.my_sig : std_logic_vector >> := '0' ;

This doesn't work...
Any idea what's the correct way ?
 

I think it's something like

u1_my_sig <= force '0';

The VHDL syntax makes my head hurt ;-)
(it looks all dyslexic being a Verilog guy)
 
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    shaiko

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Forcing something where you have no actual access
from the pins, is bad hygiene and I've seen it ruin an
ASIC development (customer did it, but who catches
the flak?).

I recommend in the interest of eventual testability,
that you design in a bidirectional port at the top
level that lets you (a) inject your own clock where
the PLL output goes and (b) monitor the PLL's output
independent of the larger circuit. You will benefit by
both, come test development time.

If you can't get at it from the pins, it's only a dream
(or nightmare).
 
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    shaiko

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You can add a force command at the beginning of the simulation to create the clock.

Example to create a 100 MHz clock:
In Modelsim/Questasim, execute this command before you start the simulation (or when you want the clock to start):

Code: 
force -freeze sim:/tb_top/top/clock 0, 1 {5 ns} -r 10 ns

You may have to adjust the path. Right-click on the signal in the simulator GUI and select "modify"->"force"->"OK" to see the correct path in the command line.

Since this is a simulator function, it will work with any VHDL version.
 
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    shaiko

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