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Want to source part of verilog file in VCS

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sanketphapale45

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Hello,
I have a standard file consisting of more thane one standard modules. but i wanted to use only 1 module from that file.
suppose

Code: 
module module_list();
module_1....
module_2....
.
.
.
module_n...
end module
I want to use module_2 and not others. When I source module_list() in vcs command i got lot many errors of unused modules. Is there any method to source only particular module/part of verilog file instead of sourcing complete file. I can't edit .sv file. I have only vcs command (make file) in my hand...

Please respond..
Thnks
,Sanket
 

Is it not possible to create your own module_list() and then source it in the make file?

Otherwise why are you accessing the complete module list? Just simulate the module which is needed.
 

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