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[SOLVED] variable size vector or array in VHDL

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rafimiet

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I have an algorithm, that generates some output bits. The number of output bits depend upon the different statistical data provided to it at input. So the number of output bits depend on the input and not on the hardware used. If I want to save the output in a vector or an array, the size of that vector or array has to change according to input. Can we have such type of vector or array in VHDL. It seems to me that such operation if possible will have some serious consequences. Can anybody help in this regard? If it is rot realizable or if it is not a good practice, then how can I proceed.
 

You are asking for a bus that changes it's size depending on the passenger amount.

The solution in logic hardware as well as in transportation is basically the same. Design for the maximal bit length/passenger count and have empty bits/seats.

In VHDL terms, you'll have a generic parameter defining the maximal word length and a numeric signal specifying how many bits are actually used.
 
Normally, the input would be provided over multiple cycles if the input is large. Likewise, the output would be provided over several cycles. However, for reasonable widths, you could have the output be a tuple: Nmax-bits for data, log2(Nmax)-bits for "number of bits valid", and possibly a 1b "this data is valid" indicator. Reasonable is based on device size and design requirements. You can also adopt this scheme for multi-cycle data, possibly adding either a "start of data" and/or "end of data" indicator. In that case, a 32b bus could transfer 100 bits as:
{!valid, !start, !end, X bits valid, X data}
{valid, start, !end, X bits valid, data[31:0]}
{valid, !start, !end, X bits valid, data[63:32]}
{valid, !start, !end, X bits valid, data[95:64]}
{valid, !start, end, 4 bits valid, data[99:96] with 28 leading/trailing bits}
{!valid, !start, !end, X bits valid, X data}

There are several variations on this generic protocol. You should document exactly what assumptions can be made. eg, if start/last can be set when valid isn't, if the number of valid bits is only used when "end" is set (as in my example). If start+end can occur at the same time, if the final output is padded with trailing random bits (or 0's) or with leading random bits (or 0's). You can then use the same style of interface throughout your design.


In general, you should try to look at having your input be provided over N-cycles, with part or all of your algorithm completing within N-cycles, and with the output being transferred within N-cycles. When an algorithm is more complex, you may need to break it into a series of steps that each complete within N-cycles. Again, this is for full bandwidth. If you don't require full bandwidth, you can buffer data and perform processing at a slower rate.
 
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