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  1. #1
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    Cadence Assura DRC error

    minimum top via enclosed by metal top 1 is 0.01micron... How to fix this error.. I am using 8Metal layer process? It appears when i place metal 6 and Top metal via top.

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  2. #2
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    Re: Cadence Assura DRC error

    min. top via is 10nm ??? Which process size? Typo?



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  3. #3
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    Re: Cadence Assura DRC error

    Quote Originally Posted by erikl View Post
    min. top via is 10nm ??? Which process size? Typo?
    I think the enclosure has to be 10nm wider than the via. either way, OP should post the actual error msg, not his interpretation of it.



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