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    Strange DRC Error with NWell Connection

    Everyone,

    I'm using the IBM cmrf8sf 130nm PDK. I've recently come upon an error I have not encountered previously and am unsure how to clear it.

    From what I can tell, it stems from the NWell connection for my PMOS devices. The Calibre DRC error reads:

    Check GR134: Floating (NW not over T3) found! - NWell must be tied down by M1.

    I have my NWell's tied down in the same way as I have in all my previous cells - I use a large NW rectangle to surround all of the pmos devices and a cell named "nwCont" to tie the well to the metal at "vdd!". When I check previous cells that use this exact approach, I do not see the error. In addition, when I run Calibre LVS, I encounter no errors, which implies that all the NWell's are properly tied to "vdd!".

    Because the foundry requires Assura DRC checks, I also run an Assura DRC, which yields 0 errors. Surprisingly, I get an error when I run Assura LVS, claiming that one of my transistors has an incorrect parameter.

    I have attached some screenshots of my layout. The first is of the full design, the second is the PMOS region, and the third is the error that appears in RVE. The coordinates that are present in RVE point to my large drawn NW region (yellow dots), the bottom left PMOS, and the nwCont NW region, respectively. I have also encountered this error in another recent design, but the layout and error is similar.

    Any advice is greatly appreciated.

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  2. #2
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    Re: Strange DRC Error with NWell Connection

    I can see the row of NW contacts at the top, but none at the bottom. Perhaps the bottom 4 transistors are too far from the top NW contacts and need closer ones, e.g. at both sides? Just an idea.



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    Re: Strange DRC Error with NWell Connection

    Thanks for the reply, erikl. I have tried this before, and the error persists. I'll give it another shot and report back.



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    Re: Strange DRC Error with NWell Connection

    The clue may lie in whatever "T3" is. I have no guess to
    offer. But maybe reading the Caliber deck and doping out
    what "T3" is derived from will lead you somewhere.



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    Re: Strange DRC Error with NWell Connection

    Ok, I think I found the error.

    I came across a similar error at the following link: https://community.cadence.com/cadenc...s/f/38/t/16451

    Looks like there is some issue with defining transistors with multiplicities>1 with this PDK. I went back to my schematic and created "m" parallel transistors for transistors I have m>1 and updated my layout, and no errors in Calibre/Assura DRC/LVS. I was planning on contacting my foundry (Mosis) about the issue, but I'll just move forward with this workaround since updating the schematic is fairly simple. If anyone comes across a solution to the actual problem with having m>1 with this PDK, I'd be interested to hear it!



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    Re: Strange DRC Error with NWell Connection

    Thank you for contributing your successful workAround! I now remember I had a similar pb. many years ago, and also found this type of workAround:

    Quote Originally Posted by tomflo View Post
    ... some issue with defining transistors with multiplicities>1 with this PDK. I went back to my schematic and created "m" parallel transistors ...
    It isn't necessary to create "m" parallel transistors in schematic, you can simply call this transistor e.g. T3<1:3> to get 3 parallel transistors T<1> , T<2> & T<3> .



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    Re: Strange DRC Error with NWell Connection

    You might experiment with whether this is a problem
    at (say) m=2, m=3... or only where high W and high
    m combine to violate "distance to tap" rules, and the
    PCell simply doesn't respect that? Or is it that using
    m= creates some "defect" in the drawn device that a
    single stripe FET doesn't have?



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    Re: Strange DRC Error with NWell Connection

    Heard from Mosis and the problem has been solved.

    In the PDK, it's required to have an M1 path (and ONLY M1 path) from and nwCont region to an nTiedown. This is typically taken care of when you connect a PMOS to NMOS using the M1 layer. The reason I never encountered this error before is because in my previous cells, designs were simpler and I was able to limit the routing between NMOS and PMOS to the M1 layer for some connections. Adjusting the paths so there are some M1 only connections between PMOS and NMOS solves the issue. Alternatively, dropping an "nTiedown" cell outside of the NW region clears the error.

    Looks like there was no issue with multiplicity - I just routed them differently apparently. Oy vey.

    Hope this is useful to others!



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