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propagation delay in fpga

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FvM said:
The application topology is still rather vague. Up to now you have described LFSRs that are clocked at different rates. How come external clocks into play?
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i am saying in original application of this project , LFSR s will not be required. Instead external source will supply dat at different rates. How this interfacing will be done is not my concern now. Since right now am not getting data from outside so in place of that i try to genrate some ransom numbers(LFSR s) considering them as source of data ... Since data will come at different rate from each source, so clocks of LFSR s are also different . Am totally confused , how to collect all this data in a memory ... Data is real time , constantly coming and i need to pu them in memory simultaneously.. If clock of memory is not synchronised with this LFSRs then how to collect all daa without loosing a single one. I just want the procedure to synchronise this clock (clock of memory) with all LFSRs.
 

So you have multiple clock inputs that each need to have LFSRs on them and you need to put all the outputs into a common memory?

How about using asynchronous clock domain crossing FIFOs for each LFSR and then use a common clock to write all the data into that other memory.

If the LFSRs are for testing purposes then the clock domain crossing to the memory should have already been taken care of, but it seems like this wasn't done.

Like was said before there is something very wrong with your design if you need to add delays to adjust your timing.

- - - Updated - - -

I suspect you also don't have a clue about "work rate" problem and will likely end up coming back to say you can't figure out how to write all those independent LFSRs into that one memory.
 

p11 said:
i am saying in original application of this project , LFSR s will not be required. Instead external source will supply dat at different rates. How this interfacing will be done is not my concern now. Since right now am not getting data from outside so in place of that i try to genrate some ransom numbers(LFSR s) considering them as source of data ... Since data will come at different rate from each source, so clocks of LFSR s are also different . Am totally confused , how to collect all this data in a memory ... Data is real time , constantly coming and i need to pu them in memory simultaneously.. If clock of memory is not synchronised with this LFSRs then how to collect all daa without loosing a single one. I just want the procedure to synchronise this clock (clock of memory) with all LFSRs.
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google "clock domain crossing" and "synchronizing FIFOS". make sure you understand the problem and the solution, don't half ass this assignment.

this is all that you need. like everyone was saying here multiple times, you don't need delays.
 

ThisIsNotSam said:
google "clock domain crossing" and "synchronizing FIFOS". make sure you understand the problem and the solution, don't half ass this assignment.
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I don't think that is the problem, the OP just doesn't understand how to architect a design based on the technology they are working with. I've seen this a lot more in recent years when interviewing less experienced engineers. Heavy on theory, no practical understanding of architecture and implementation and for some reason they always get into thought-lock on only one way of doing something. In this case it was: "I need to line up all the outputs to match the destination clock".

OP, so how do you expect to handle two (or more) LFSRs needing to write data into the memory simultaneously on the exact SAME clock?
 

Right, there is that too. OP is in for a ride.
 

ads-ee said:
I don't think that is the problem, the OP just doesn't understand how to architect a design based on the technology they are working with. I've seen this a lot more in recent years when interviewing less experienced engineers. Heavy on theory, no practical understanding of architecture and implementation and for some reason they always get into thought-lock on only one way of doing something. In this case it was: "I need to line up all the outputs to match the destination clock".

OP, so how do you expect to handle two (or more) LFSRs needing to write data into the memory simultaneously on the exact SAME clock?
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yes for that i tried to generate a clock internally synchronised with all clocks of lfsrs ... how i did it is explained above... anyway thanks..
 

p11 said:
yes for that i tried to generate a clock internally synchronised with all clocks of lfsrs ... how i did it is explained above... anyway thanks..
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Yup, thought lock...only sees one way of doing something. more clocks and delays to line up stuff.

FYI, that is the wrong way to do this. the right way was explained in some of the previous posts.

And here is a hint for the unresolved multiple simultaneous accesses issue....arbitration
 

@P11:

In many systems, a system clock is used for processing. "valids" or "enables" are passed from block to block to enable processing at each block. As a result, you might have an input that has 1 valid per 3.5 cycles. For example, 3 cycles between valid followed by 4 cycles between valid. This is sometimes called the "cadence" of the input. A similar system could have 1 cycle between valid and then 6 before the next. Or maybe three valid cycles in a row followed by 11 invalid.

You can use the clock domain crossing fifos for this purpose.
 

vGoodtimes said:
@P11:

In many systems, a system clock is used for processing. "valids" or "enables" are passed from block to block to enable processing at each block. As a result, you might have an input that has 1 valid per 3.5 cycles. For example, 3 cycles between valid followed by 4 cycles between valid. This is sometimes called the "cadence" of the input. A similar system could have 1 cycle between valid and then 6 before the next. Or maybe three valid cycles in a row followed by 11 invalid.







You can use the clock domain crossing fifos for this purpose.
Click to expand...

thanks a lot sir ... i am trying that and hope to succeed .
 

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