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What stage to use TimeQuest and what netlist to use with it?

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matrixofdynamism

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TimeQuest needs to have a timing netlist so we can apply the timing constraints. However, the timing netlist could be post map or post fit. These options mean:

Post-map— The TimeQuest analyzer performs timing analysis on a timing netlist that contains synthesis information only.
Post-fit— The TimeQuest analyzer performs timing analysis on a timing netlist that contains physical synthesis optimizations and fitting.

How do I know which one to use? Do I just do synthesis of the design and then apply the timing constraints on post-map netlist and then perform full compilation OR Compile the design, then apply timing constraints on post-fit netlist and then compile all over again?

What is the difference?
 

usually, you just provide an sdc file, and the sdc constraints are used in the fitter and timequest. The fitter needs the constraints to help make the design meet timing, and Timequest needs to be run after the fit to ensure the design met timing. This is what you would do in a normal flow.
 

Ok, then the question should be changed slightly. When do I apply timing constraints?
 

aha, so I run the analysis and synthesis and then I apply the timing constraints e.g create_clock, derive_clock_uncertainity, derive_pll_clock, set_input_delay, set_output_delay e.t.c

Will I have to change any of these after I have run the fitter? Could you give an example of when I may need to change them after fitter? Thanks :)
 

You shouldn't have to (or need to) change them after synthesis. The only reason you might have is because you use different synthesis vs. implementation timing constraints for the clock in an attempt to improve the Fmax of the design so it meets timing easier during implementation (though you'll find mixed results doing this, more often it doesn't help at all).
 

Its much easier just to generate a single constraints file and include it with the design. The .sdc file is just a tcl file that allows you to run tcl commands (for altera at least), like applying sdc constraints only to the fitter if you really have to (for example overconstraining the design during the fit to try and make it meet timing during timing analysis). But as a start, all you need are:

1. Your clocks
2. IO Delays
3. Any multi-cycle constraints and false paths

see this for a applying constraints to different stages from a single file:

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd06062011_944.html
 

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