Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[Place 30-140] Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component

Status
Not open for further replies.

beginner_EDA

Full Member level 4
Joined
Aug 14, 2013
Messages
191
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
3,854
Hi,
on Intermet I read that this error occurs when GT common is not in the same quad as GT channel:

I was using following reference design:
https://www.xilinx.com/support/documentation/application_notes/xapp1199-smpte2022-56-over-ip.pdf

where SDI Transceiver was already set with FMC which connect daughter card and I don't have to do any setting for transceiver.

Now I want to use SFP module having SDI in/out with different custom board. I map the pins accordingly but then I am getting this error(attachment).
but don't know how to set GT common in the same channel quad. Any hints? where I can change this setting?
 

Attachments

  • error_tcl.txt
    13.3 KB · Views: 41

You can do manual changes to the reference design to suite your needs.
 

Hi,
In reference design I didn't find Transceiver setting like here:
https://www.xilinx.com/support/docu...notes/xapp1200-k7-xcvr-wiz-example-design.pdf

so, I don't know how to do that.

- - - Updated - - -

The situtaion is like in attachment.
and in .xdc constraint file:

clock:
set_property PACKAGE_PIN G8 [get_ports FMC_HPC_GBTCLK0_M2C_C_P]
set_property PACKAGE_PIN G7 [get_ports FMC_HPC_GBTCLK0_M2C_C_N]

set_property PACKAGE_PIN J8 [get_ports FMC_HPC_GBTCLK1_M2C_C_P]
set_property PACKAGE_PIN J7 [get_ports FMC_HPC_GBTCLK1_M2C_C_N]

For 4 SDI:
Transceiver:
set_property PACKAGE_PIN K1 [get_ports FMC_HPC_DP3_C2M_N]
set_property PACKAGE_PIN K2 [get_ports FMC_HPC_DP3_C2M_P]
set_property PACKAGE_PIN J3 [get_ports FMC_HPC_DP2_C2M_N]
set_property PACKAGE_PIN J4 [get_ports FMC_HPC_DP2_C2M_P]
set_property PACKAGE_PIN H1 [get_ports FMC_HPC_DP1_C2M_N]
set_property PACKAGE_PIN H2 [get_ports FMC_HPC_DP1_C2M_P]
set_property PACKAGE_PIN F1 [get_ports FMC_HPC_DP0_C2M_N]
set_property PACKAGE_PIN F2 [get_ports FMC_HPC_DP0_C2M_P]



common:
set_property LOC GTXE2_COMMON_X0Y3 [get_cells VOIP/i_kc705_sdi_wrapper/gtxe2_common_0/gtxe2_common_i]



similarly for 10Gig:
Transceiver:
set_property PACKAGE_PIN R3 [get_ports kc705_SFP_RX_N]
set_property PACKAGE_PIN R4 [get_ports kc705_SFP_RX_P]
set_property PACKAGE_PIN N3 [get_ports kc705_SFP_TX_N]
set_property PACKAGE_PIN N4 [get_ports kc705_SFP_TX_P]

set_property LOC GTXE2_COMMON_X0Y2 [get_cells VOIP/ten_gig_block_kc705/GEN_10BASER_SHARED.i_10baseR_pcs_pma/U0/ten_gig_eth_pcs_pma_gt_common_block/gtxe2_common_0_i]
 

Attachments

  • transceiver.jpg
    transceiver.jpg
    59.8 KB · Views: 82

but don't know how to set GT common in the same channel quad. Any hints? where I can change this setting?

Did you reconfigure the IP core using the wizard. The placement constraints used for the transceivers is physically numbered differently than the documentation and the wizard would suggest. The simplest way to use the transceivers (and move them to a different set of pins) is to just reconfigure the core in the wizard.
 

Did you reconfigure the IP core using the wizard.

Hi, there is no transceiver wizard available for this reference design. but there are 2 files available for GT common block.

10 gig side read only file:

set_property LOC GTXE2_COMMON_X0Y2 [get_cells VOIP/ten_gig_block_kc705/GEN_10BASER_SHARED.i_10baseR_pcs_pma/U0/ten_gig_eth_pcs_pma_gt_common_block/gtxe2_common_0_i]

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
gtxe2_common_0_i : GTXE2_COMMON
    generic map
    (
            -- Simulation attributes
            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
            SIM_QPLLREFCLK_SEL   => ("001"),
            SIM_VERSION          => "4.0",
 
 
       ------------------COMMON BLOCK Attributes---------------
        BIAS_CFG                                =>     (x"0000040000001000"),
        COMMON_CFG                              =>     (x"00000000"),
        QPLL_CFG                                =>     (x"0680181"),
        QPLL_CLKOUT_CFG                         =>     ("0000"),
        QPLL_COARSE_FREQ_OVRD                   =>     ("010000"),
        QPLL_COARSE_FREQ_OVRD_EN                =>     ('0'),
        QPLL_CP                                 =>     ("0000011111"),
        QPLL_CP_MONITOR_EN                      =>     ('0'),
        QPLL_DMONITOR_SEL                       =>     ('0'),
        QPLL_FBDIV                              =>     (QPLL_FBDIV_IN),
        QPLL_FBDIV_MONITOR_EN                   =>     ('0'),
        QPLL_FBDIV_RATIO                        =>     (QPLL_FBDIV_RATIO),
        QPLL_INIT_CFG                           =>     (x"000006"),
        QPLL_LOCK_CFG                           =>     (x"21E8"),
        QPLL_LPF                                =>     ("1111"),
        QPLL_REFCLK_DIV                         =>     (1)
        
    )
    port map
    (
        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
        DRPCLK                          =>      tied_to_ground_i,
        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
        DRPDO                           =>      open,
        DRPEN                           =>      tied_to_ground_i,
        DRPRDY                          =>      open,
        DRPWE                           =>      tied_to_ground_i,
        ---------------------- Common Block  - Ref Clock Ports ---------------------
        GTGREFCLK                       =>      tied_to_ground_i,
        GTNORTHREFCLK0                  =>      tied_to_ground_i,
        GTNORTHREFCLK1                  =>      tied_to_ground_i,
        GTREFCLK0                       =>      gt0_gtrefclk0_common_in,
        GTREFCLK1                       =>      tied_to_ground_i,
        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
        ----------------------- Common Block - Clocking Ports ----------------------
        QPLLOUTCLK                      =>      gt0_qplloutclk_i,
        QPLLOUTREFCLK                   =>      gt0_qplloutrefclk_i,
        REFCLKOUTMONITOR                =>      open,
        ------------------------- Common Block - QPLL Ports ------------------------
        QPLLDMONITOR                    =>      open,
        QPLLFBCLKLOST                   =>      open,
        QPLLLOCK                        =>      gt0_qplllock_out,
        QPLLLOCKDETCLK                  =>      '0',
        QPLLLOCKEN                      =>      tied_to_vcc_i,
        QPLLOUTRESET                    =>      tied_to_ground_i,
        QPLLPD                          =>      tied_to_ground_i,
        QPLLREFCLKLOST                  =>      open,
        QPLLREFCLKSEL                   =>      "001",
        QPLLRESET                       =>      gt0_qpllreset_in,
        QPLLRSVD1                       =>      "0000000000000000",
        QPLLRSVD2                       =>      "11111",
        --------------------------------- QPLL Ports -------------------------------
        BGBYPASSB                       =>      tied_to_vcc_i,
        BGMONITORENB                    =>      tied_to_vcc_i,
        BGPDB                           =>      tied_to_vcc_i,
        BGRCALOVRD                      =>      "00000",
        PMARSVD                         =>      "00000000",
        RCALENB                         =>      tied_to_vcc_i
 
    );



SDI side:
set_property LOC GTXE2_COMMON_X0Y3 [get_cells VOIP/i_kc705_sdi_wrapper/gtxe2_common_0/gtxe2_common_i]

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
GTXE2_COMMON #
    (
            // Simulation attributes
            .SIM_RESET_SPEEDUP   (WRAPPER_SIM_GTRESET_SPEEDUP),
            .SIM_QPLLREFCLK_SEL  (3'b001),
            .SIM_VERSION         ("4.0"),
 
 
           //----------------COMMON BLOCK Attributes---------------
            .BIAS_CFG                               (64'h0000040000001000),
            .COMMON_CFG                             (32'h00000000),
            .QPLL_CFG                               (27'h06801C1),
            .QPLL_CLKOUT_CFG                        (4'b0000),
            .QPLL_COARSE_FREQ_OVRD                  (6'b010000),
            .QPLL_COARSE_FREQ_OVRD_EN               (1'b0),
            .QPLL_CP                                (10'b0000011111),
            .QPLL_CP_MONITOR_EN                     (1'b0),
            .QPLL_DMONITOR_SEL                      (1'b0),
            .QPLL_FBDIV                             (QPLL_FBDIV_IN),
            .QPLL_FBDIV_MONITOR_EN                  (1'b0),
            .QPLL_FBDIV_RATIO                       (QPLL_FBDIV_RATIO),
            .QPLL_INIT_CFG                          (24'h000006),
            .QPLL_LOCK_CFG                          (16'h21E8),
            .QPLL_LPF                               (4'b1111),
            .QPLL_REFCLK_DIV                        (1)
 
    )
    gtxe2_common_i
    (
        //----------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
        .DRPADDR                        (tied_to_ground_vec_i[7:0]),
        .DRPCLK                         (tied_to_ground_i),
        .DRPDI                          (tied_to_ground_vec_i[15:0]),
        .DRPDO                          (),
        .DRPEN                          (tied_to_ground_i),
        .DRPRDY                         (),
        .DRPWE                          (tied_to_ground_i),
        //-------------------- Common Block  - Ref Clock Ports ---------------------
        .GTGREFCLK                      (GTGREFCLK_IN),
        .GTNORTHREFCLK0                 (GTNORTHREFCLK0_IN),
        .GTNORTHREFCLK1                 (GTNORTHREFCLK1_IN),
        .GTREFCLK0                      (GTREFCLK0_IN),
        .GTREFCLK1                      (GTREFCLK1_IN),
        .GTSOUTHREFCLK0                 (GTSOUTHREFCLK0_IN),
        .GTSOUTHREFCLK1                 (GTSOUTHREFCLK1_IN),
        //----------------------- Common Block -  QPLL Ports -----------------------
        .QPLLDMONITOR                   (),
        //--------------------- Common Block - Clocking Ports ----------------------
        .QPLLOUTCLK                     (QPLLOUTCLK_OUT),
        .QPLLOUTREFCLK                  (QPLLOUTREFCLK_OUT),
        .REFCLKOUTMONITOR               (),
        //----------------------- Common Block - QPLL Ports ------------------------
        .QPLLFBCLKLOST                  (),
        .QPLLLOCK                       (QPLLLOCK_OUT),
        .QPLLLOCKDETCLK                 (QPLLLOCKDETCLK_IN),
        .QPLLLOCKEN                     (tied_to_vcc_i),
        .QPLLOUTRESET                   (tied_to_ground_i),
        .QPLLPD                         (tied_to_ground_i),
        .QPLLREFCLKLOST                 (QPLLREFCLKLOST_OUT),
        .QPLLREFCLKSEL                  (3'b001),
        .QPLLRESET                      (QPLLRESET_IN),
        .QPLLRSVD1                      (16'b0000000000000000),
        .QPLLRSVD2                      (5'b11111),
        //------------------------------- QPLL Ports -------------------------------
        .BGBYPASSB                      (tied_to_vcc_i),
        .BGMONITORENB                   (tied_to_vcc_i),
        .BGPDB                          (tied_to_vcc_i),
        .BGRCALOVRD                     (5'b11111),
        .PMARSVD                        (8'b00000000),
        .RCALENB                        (tied_to_vcc_i)
 
    );



How to reconfigure here?
 

The transceivers use dedicated clock routes so you'll have to tailor the above code to suite your specific device and board design.
I remember having to change the QPLLREFCLKSEL setting (Clock MUX selector).
Please consult Xilinx's MIG 7 UG.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top