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[SOLVED] Does adding timing constraints needs rerunning synth and implementation ?

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UltraGreen

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I am using Vivado 2016.2 , and virtex ultrascale.
My design is successfully implemented, now I want to increase the frequency of the design by modifying mmcm out clock from 50 MHz to 75 MHz, or if I need to add some false path or multicycle path constraint in the the implemented design, then in these cases can I force up to date the design and avoid rerunning the implementation run and only rerun the "report timing summary " ?
will I get updated timing summary ?
 

You need to make the necessary updates to your xdc files and then re-run impl process.
You may also take a look at the slack value and make an estimate if timings will be met at 75MHz or not.
 
UltraGreen said:
I am using Vivado 2016.2 , and virtex ultrascale.
My design is successfully implemented, now I want to increase the frequency of the design by modifying mmcm out clock from 50 MHz to 75 MHz, or if I need to add some false path or multicycle path constraint in the the implemented design, then in these cases can I force up to date the design and avoid rerunning the implementation run and only rerun the "report timing summary " ?
will I get updated timing summary ?
Click to expand...

If you implemented the design with a 50 MHz constraint, it is virtually a given that the design will NOT run at 70 MHz. The tools will typically implement the design by meeting timing without a large amount of slack.

The easiest way to determine if the current design (with 50 MHz constraint) will work at 70 MHz is to look at the current timing report and see if there is more than 5.7 ns of positive slack on the worst case path.

Note using false path or multicycle paths to "cover up" violations is going to leave you with a design that will probably not work.
 

FWIW, if you change the clock you need to re-run timing.

Specifically, there are lower bounds checks on PLLs and MMCMs that can be affected by lowering a clock. This means lowering a clock could result in an infeasible design -- despite timing constraints being easier to meet.

Increasing a clock is an obvious "rerun timing analysis".




also, strong-agree with ads-ee. false-path should only be used for LED's. multi-cycle path is more complex as simulation doesn't understand the concept.
 

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