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[SOLVED] is it safe to use 2 separate buffer for clock domain crossing?

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LatticeSemiconductor

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hi all,

i have a stream consisting of data and address, synchronous to clk1 . I am buffering them in FIFOs to pass the data synchrounos to clk2. address and data are stored in separate FIFOs, bc the data read is half the width of the data written.

The fifos are both on the same clocks, clk1 (write) and clk2 (read). Can it still be that their watermark on clk2 domain are updated at different clock cycles?
 

Can it still be that their watermark on clk2 domain are updated at different clock cycles?
Click to expand...
Yes it can.
Therefore it's safe only if you evaluate the empty/full flags of both FIFO before reading/writing.

I'd use one FIFO in such a case.
It'll consume less logic and probably will have a higher Fmax.
 
LatticeSemiconductor said:
address and data are stored in separate FIFOs, bc the data read is half the width of the data written.
Click to expand...

shaiko said:
I'd use one FIFO in such a case.
It'll consume less logic and probably will have a higher Fmax.
Click to expand...

Based on the requirements of reading data with a 1:2 ratio with writing means you needed to use width conversion and therefore had two FIFOs. You can still use shaiko's suggestion of one FIFO but you will have to do the 1:2 width conversion outside the FIFO itself for just the data.
 

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