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Assura DRC error cmhv7sf

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Alpacca

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Hi there,

I'm making an OTA layout in Cadence, ams 0.18um (cmhv7sf). The only DRC error I have is about I/O wirebond - it says that some transistors don't have body contact while there are n-well contacts. When there where contacts on the left and right side errors where the same.
I_O_wirebond.pngota.png

Any hints?
 

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