luoyanghero
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env:vivado201603, modelsim 10.4 se win64
I have used modelsim compiled vivado library, and simulated a core generated fifo
using modelsim, it is OK.
Now I core_gen a ddr4 with axi interface, I use modelsim to simulate, failed.
1.modelsim command script as follow:
2.The error as follows:
3.I know in modelsim need add a option to include xilinx lib, for example a
fifo: '-L fifo_generator_v13_1_2 '.
But I don't know the specified lib for
ddr4. I tried to include all xilinx lib, it not success.
4.Follow the errors, I try to add module ddr4_0_ddr4 in the relative files:
There are more errors than before.
5.I try to use vivado simulating ddr4, it can work.
How should I do in modelsim environment to simulate ddr4?
I have used modelsim compiled vivado library, and simulated a core generated fifo
using modelsim, it is OK.
Now I core_gen a ddr4 with axi interface, I use modelsim to simulate, failed.
1.modelsim command script as follow:
Code Verilog - [expand]
2.The error as follows:
Code dot - [expand]
3.I know in modelsim need add a option to include xilinx lib, for example a
fifo: '-L fifo_generator_v13_1_2 '.
But I don't know the specified lib for
ddr4. I tried to include all xilinx lib, it not success.
4.Follow the errors, I try to add module ddr4_0_ddr4 in the relative files:
Code dot - [expand]
There are more errors than before.
5.I try to use vivado simulating ddr4, it can work.
How should I do in modelsim environment to simulate ddr4?
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