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  1. #1
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    How to fix intra clock timing violation

    Hello all ,

    There are times, when I am not allowed to change the RTL, and all the clocking structure in the design are already optimized.
    Still I face situations where I have negative slack ( setup as well as hold )
    Some times by trying few strategies in Vivado, the tool solves the timing violations, but what if it doesn't ?

    Question 1 : Can I always set false path for violation occurring at inter-clock-path ? ( provided , CDC is taken care in RTL )

    Question 2 : How to solve Intra-clock-path timing violations ( setup and hold )

    Thanks in advance..

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  2. #2
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    Re: How to fix intra clock timing violation

    Can I always set false path for violation occurring at inter-clock-path ? ( provided , CDC is taken care in RTL )
    Yes.

    How to solve Intra-clock-path timing violations ( setup and hold )
    Provided that you follow good FPGA design practices (mainly using dedicated clock routes) - hold time violations will rarely occur.
    Setup violations are common and can be mitigated by pipelining (adding registers between combinatoric logic blocks), avoiding high fanout buses, smart pin location assignments and working at a lower temperature.
    When these don't help - you simply have to lower the frequency of your design.


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  3. #3
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    Re: How to fix intra clock timing violation

    Quote Originally Posted by UltraGreen View Post
    Question 1 : Can I always set false path for violation occurring at inter-clock-path ? ( provided , CDC is taken care in RTL )
    No. There is a constraint for each CDC. For example, gray code will fail if bits arrive with more than one cycle of skew. Other protocols can be similar. Vivado now has set_bus_skew and set_data_check for this purpose. Synchronizers should have the ASYNC_REG property set. See UG903 and UG912 if you are using Vivado.


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