Using SRAM in the Altera DE2-115 board

I want to use the SRAM on the Altera DE2-115 board in VHDL design. I am aware that it is possible to use a ready made memory controller in a Qsys system. However, as far as I understand that memory controller in Qsys is for use with a Nios II and Avalon memory mapped bus.

I only need to use a VHDL state machine to control the memory controller. Therefore, I am not sure if I can create a Qsys system with this memory controller without a Nios II.

Is writing my own memory controller the only way?

You can implement the controller in Qsys, export the signals to your HDL and connect it to your application SM in the top level of your design.
Another solution (which I like less) will be to write your application SM in HDL and import it to Qsys.
In either way, there's no need to write your own controller.

OK, so I select the memory controller from the IP catalog which opened a Qsys like window rather than a megawizard type window like we used to get when we select PLL and memory blocks. Why is that?
Now I select the parameters and then click generate HDL which asks me about synthesis files and simulation files. I select VHDL in both. Now I get a raft of files created in folder named simulation and another folder named synthesis. I am not sure what to do next.

There are VHD files with same name as I specified for my memory controller when I chose it, when I open them they just seem to internally instantiate the memory controller and connect it to the top level. However, there is no library file or otherwise at that explains where the memory controller itself is defined. If I try to carry out simulation in ModelSim it says that the component "is not bound". In Quartus however, it is able to figure out where the files are due to some .qip file which is a tcl script with a lot of lines, also found inside the synthesis folder.

Usually with a memory block IP, we get a megawizard window in which we click next and next until it reaches the end. There is no "Generate HDL" for it. The same is true for PLL. There we have a very clear distinct obvious manifest HDL file that we can compile and instantiate in our design top level to include that PLL or memory block into the design. However, with this specific case of memory controller it is creating a lot of files and it is not clear why, and how to get what I want.

OK, so I select the memory controller from the IP catalog which opened a Qsys like window rather than a megawizard type window like we used to get when we select PLL and memory blocks. Why is that?
Now I select the parameters and then click generate HDL which asks me about synthesis files and simulation files. I select VHDL in both. Now I get a raft of files created in folder named simulation and another folder named synthesis. I am not sure what to do next.

Click to expand...

Some components can be generated from either Qsys or the IP catalog. Others can be generated only from Qsys. What you should do is add the QIP to your project...
This TCL file will add all the necessary files packed under it.

OK so I was confused for the last 2 days on what is going and what figured out what the actual problem is that is making it difficult to follow Altera documentation. It seems that there is a bug in the program.

I am using Altera Quartus II 15.0 64 bit.

I select SRAM/SSRAM controller from the IP catalog. Then I click generate HDL and select Verilog for the "simulation" tab. Now I repeat the same process but select VHDL instead of verilog.

I notice that when I select VHDL I do not get a folder called "submodules" in the simulation folder. However, when I select Verilog, I do. The submodules folder is created and it contains a .v file containing source code for the SRAM/SSRAM controller. Why are different files being generated in the two cases?

This seems to be a bug in the program.

matrixofdynamism said:

OK so I was confused for the last 2 days on what is going and what figured out what the actual problem is that is making it difficult to follow Altera documentation. It seems that there is a bug in the program.

I am using Altera Quartus II 15.0 64 bit.

I select SRAM/SSRAM controller from the IP catalog. Then I click generate HDL and select Verilog for the "simulation" tab. Now I repeat the same process but select VHDL instead of verilog.

I notice that when I select VHDL I do not get a folder called "submodules" in the simulation folder. However, when I select Verilog, I do. The submodules folder is created and it contains a .v file containing source code for the SRAM/SSRAM controller. Why are different files being generated in the two cases?

This seems to be a bug in the program.

Click to expand...

Altera do all of their new IP development in (System)Verilog. When you ask for VHDL, often you get the IP in verilog and a VHDL wrapper.

I have felt that too. However, it is clear that the RTL files for the memory controller are not generated when I select VHDL for simulation. They are still generated in the folder named synthesis but not in folder named simulation. In both cases a folder named submodules is to be created inside of them.