reddvoid
Junior Member level 3
Hi,
Typical power consumed by a clock tree in the design is around 40-45%
What is the typical or on an average power consumed by combinational logic cells in the design after pnr.
Thanks
Typical power consumed by a clock tree in the design is around 40-45%
What is the typical or on an average power consumed by combinational logic cells in the design after pnr.
Thanks