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    Average Power consumed by combinational logic in IC : after pnr ; ptpx

    Hi,
    Typical power consumed by a clock tree in the design is around 40-45%
    What is the typical or on an average power consumed by combinational logic cells in the design after pnr.


    Thanks

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    Re: Average Power consumed by combinational logic in IC : after pnr ; ptpx

    sorry, this is too vague. and your premise is wrong. I have just finished a chip where the clock tree was 10%.



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    Re: Average Power consumed by combinational logic in IC : after pnr ; ptpx

    Quote Originally Posted by ThisIsNotSam View Post
    sorry, this is too vague. and your premise is wrong. I have just finished a chip where the clock tree was 10%.
    Hi, Thanks for the reply.
    I am new to PnR please bear with me , Can you give number of standard cells and macro numbers in your design...What would be the % of power consumed by CT for the design with like 300,000 standard cells and around 100 macros. I saw in few designs the CT power was around 40-45% and I assumed this is common trend cuz maximum switching activity ll be in clock tree compared to other parts.

    Whats the main factor which decides power consumed by CT compared to total power ?

    Thank you.



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    Re: Average Power consumed by combinational logic in IC : after pnr ; ptpx

    It's all about transition density, and gate by gate this is
    widely variable.

    Clock tree vs total, that's architectural. How much is
    always-clocked registers / FFs, how much is gated-
    clock, how much is combo logic? Nobody's answer
    will be the same as yours, unless their chip design
    is the same as yours. Assessing the similarity of
    basis, for any answer you get, is on you.



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    Re: Average Power consumed by combinational logic in IC : after pnr ; ptpx

    Quote Originally Posted by dick_freebird View Post
    It's all about transition density, and gate by gate this is
    widely variable.

    Clock tree vs total, that's architectural. How much is
    always-clocked registers / FFs, how much is gated-
    clock, how much is combo logic? Nobody's answer
    will be the same as yours, unless their chip design
    is the same as yours. Assessing the similarity of
    basis, for any answer you get, is on you.
    Okay, we can make a design which can consume wide range of CT power It depends on all these factors but typical IC blocks have on an average certain % of combinational cells and certain % of registers and hard macros, can't we assume in general in designes used in industry CT ll consume almost 50% of power , cuz I read same thing in multiple sources.
    Example:
    " clock network is responsible for more than half the power consumed on any chip " this is from the source http://semiengineering.com/the-troub...h-clock-trees/

    Click image for larger version. 

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    If not, I don't understand why here it is assumed that CT consumes more-than 50% of total power.

    Thank you



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    Re: Average Power consumed by combinational logic in IC : after pnr ; ptpx

    Guys, please, have some level of critical thinking. Of course 50% is not always the case.
    Clock trees can be the bottleneck of your design, or it can be a meaningless blip on the radar. We can talk about CTS and its goals (slew, delay, skew). If you have relaxed goals for these, then your clock tree is going to be very easy.



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    Re: Average Power consumed by combinational logic in IC : after pnr ; ptpx

    Quote Originally Posted by reddvoid View Post
    Hi,
    Typical power consumed by a clock tree in the design is around 40-45%
    What is the typical or on an average power consumed by combinational logic cells in the design after pnr.


    Thanks
    This percentage is just a reference number.
    It is meaningless that your design's power consumption should be in any typical range.
    To improve one's brain, the doors are needed over the keys.



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