[SOLVED] current capacity of CMOS devices

Hi everyone!
I'm thinking if there is a capacity for maximum current allowed to flow through a device of ratio w/l, like the one for metal layers?
I mean if I have a device which should carry 100 mA, is there a minimum w/l for that? think the device is not biased and will be used as a switch. Is it enough just to calculate the w/l for a typical Vod with the square low?

Well, of course there's a W direct dependence of current
and there's a minimum L, which perhaps will be driven up
by contrary concerns such as ruggedness (presumably all
of this current is going on and off chip to ugly places).

There's much more to it than raw W in any case. On modern
technologies linewidths (minimum) are tiny and so is current
carrying capacity of the minimum trace. Meaning that if
you had an infintely wide FET you would never be able to
reliably pass more than milliamps regardless, without fusing
the metal or greatly shortening its life. So you must move
to multifinger device structures. Pin-connected devices
also must follow ESD rules which will impose a silicide-free
"ballast" region at S/D. You'll complain because now the
FET has worse on-resistance. But these "useless" areas are
a good place to put fat metal. Beware also letting current
enter and exit at the same end, this causes debiasing along
the source stripe and concentrates current, with thermal
and performance negatives. Better is to let the S, D metal
be only "straps" and take current out on the next layer
with interdigitated fat metal. Most efficient is likely to be
just as fat as barely doesn't trigger the next level of
"wide metal spacing" or "slotting" rules.

Your design rules will give you a mA/um rule for each layer,
a mA/contact rule for each contact / via layer and so on.
This may fall to you as an inspection task, or in ultra-
modern kits and tools maybe Mother Software will tell you
when you've been naughty.