[SOLVED] Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component pair is not placed

Hi guys
I am working on a project. I am receiving these errors and I don't know how I should fix them. could you tell me what I should do?
thanks a lot.

[Place 30-140] Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component pair is not placed in a routable site pair. The GTXE_COMMON component can use the dedicated path between the GTXE_COMMON and the GTXE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets transmitter/GTX/gt0_qplloutclk_i] >

transmitter/GTX/gtxe2_common_0_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y0
transmitter/GTX/gt0_k7gtx_sdi_wrapper_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y7

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_gt_bufg
Status: PASS
Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
receiver/GTX/gt0_k7gtx_sdi_wrapper_i/gtxe2_i (GTXE2_CHANNEL.RXOUTCLK) is locked to GTXE2_CHANNEL_X0Y5
receiver/BUFGRX1 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y29

Clock Rule: rule_gtxcommon_gtxchannel
Status: PASS
Rule Description: A GTXCommon driving a GTXChannel must both be in the same clock region
receiver/GTX/gtxe2_common_0_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y1
receiver/GTX/gt0_k7gtx_sdi_wrapper_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y5

Clock Rule: rule_bufds_bufg
Status: PASS
Rule Description: A BUFDS driving a BUFG must be placed on the same half side (top/bottom) of the device
MGTCLKIN0 (IBUFDS_GTE2.ODIV2) is locked to IBUFDS_GTE2_X0Y3
receiver/BUFG74_25 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
transmitter/BUFG74_25 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y30

Clock Rule: rule_bufds_gtxchannel_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTXChannel must both be placed in the same or adjacent clock region
(top/bottom)
MGTCLKIN0 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y3
receiver/GTX/gt0_k7gtx_sdi_wrapper_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y5
transmitter/GTX/gt0_k7gtx_sdi_wrapper_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y7

Clock Rule: rule_bufds_gtxcommon_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTXCommon must both be placed in the same or adjacent clock region
(top/bottom)
MGTCLKIN0 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y3
receiver/GTX/gtxe2_common_0_i (GTXE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y1
transmitter/GTX/gtxe2_common_0_i (GTXE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y0

Clock Rule: rule_gt_bufg
Status: PASS
Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
transmitter/GTX/gt0_k7gtx_sdi_wrapper_i/gtxe2_i (GTXE2_CHANNEL.RXOUTCLK) is locked to GTXE2_CHANNEL_X0Y7
and transmitter/BUFGRX1 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y27

I am working on a project.

Click to expand...

Missing information:

Which FPGA involved?
Board is development kit (which) or custom design?

If development kit, you probably didn't manage to use the existing clocks as intended. If custom design, there may be required clock signals missing.

thanks for the comment.
I am using a custom design with Kintex7 fpga.

I might see the issue. There are two possibilities I see.

Firstly, the numbering scheme is weird for Xilinx devices. Needlessly weird really. The FPGA pin names are based on something relevant to Xilinx, but require a lookup table to determine the GT tile location for a given device. It is possible you've managed to connect the wrong common tile to the wrong channel.

Second, there is clock chaining that may be required. The Kintex allows the reference clock to be sourced from other tiles that are near enough. I'm not sure if the tools can pick this up. You may need to place the other gtx common tiles in an appropriate mode. eg, muxes set to pass through, pll powered down, io buffer powered down, etc... This gets the clock to the correct clock region.

Can you provide any GT data and clock locations?

szczepeka said:

Can you provide any GT data and clock locations?

Click to expand...

At the minimum you should supply the GT tile location constraints, the GT pin locations, the reference clock locations for the GT tiles, the exact part number of the K7 FPGA with the package information, and any information on how your planned clocking scheme is done (what vGoodtimes was discussing).