lh-
Member level 1
i'm writing verilog code vending machine. i have 4 'columns' for each product, each of which is a 2D array. i need to check if there are still products left, if so, return that product and shift the bits so that i have a 0 for the returned product. first a coin is inserted, then a column (i.e. the 2D array) is selected. how should i do the checking in if()? and what should i shift? i don't get how to do this since it's a 2D array. should i 'walk over' every element of the array? or what?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 module vending_machine(vend,change,coin,column,clk,rst); output reg vend; output reg [2:0] change; input [2:0] coin; input clk; input rst; parameter IDLE=2'b0; parameter PROCESSING=2'b1; parameter VENDING=2'b10; parameter ONE=3'b1; parameter TWO=3'b10; parameter THREE=3'b11; parameter FOUR=3'b100; parameter COL_A=3'b1; parameter COL_B=3'b10; parameter COL_C=3'b11; parameter COL_D=3'b100; reg [3:0] A[0:4]; reg [3:0] B[0:4]; reg [3:0] C[0:4]; reg [3:0] D[0:4]; reg [1:0] state; reg [1:0] next_state; reg [1:0] column; integer i; always @(posedge rst) begin state=IDLE; coin=0; change=0; column=0; for(i=0; i<4; i=i+1) begin A[i]=4'b1111; B[i]=4'b1111; C[i]=4'b1111; D[i]=4'b1111; end end always @(posedge clk) begin case(state) IDLE: begin if(coin) begin next_state=PROCESSING; end else begin next_state=state; end end PROCESSING: begin case(coin) ONE: begin case(column) COL_A: begin if() begin vend=1; change=0; <shift> end else begin vend=0; change=coin; end end default: begin $display("err"); end endcase end
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