Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I've looked through several manufacturers data sheets for this and similar devices and they all show the internal logic gate structure.
The truth table is what you posted so I'm not sure what else you could want.
I've looked through several manufacturers data sheets for this and similar devices and they all show the internal logic gate structure.
The truth table is what you posted so I'm not sure what else you could want.
If you follow the instructions in your text book or lecture script, you should be able to draw a Karnaugh map from the given truth table. Please notice that the two enable inputs have a simple logic function. It doesn't make much sense to include them in the Karnaugh map.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
