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    What is RTL Signoff in FPGA/ASIC design flow

    Hi,

    What is RTL signoff. Where is this step(s) done in FPGA/ASIC design flow - after synthesis and before place and route or elsewhere? Is there any free tool available for the same?

    Thanks,
    Hobbyiclearner.

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    Re: What is RTL Signoff in FPGA/ASIC design flow

    RTL freeze is when the code is considered stable and final. It will probably be synthesised many times before that, to have an idea of how it performs. It will also be synthesised one last time after, and that is the netlist that will be sent to physical implementation.



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    Re: What is RTL Signoff in FPGA/ASIC design flow

    In real life, PnR engineers start with some work before the final version of RTL is available. But they can accept changes up to a certain time (in reality a synth & dft inserted netlist).
    As per my knowledge RTL signoff or RTL freeze, is that version of RTL after which no more changes will be allowed in it.
    Otherwise it would be very costly for the PnR.
    FPGA enthusiast!



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    Re: What is RTL Signoff in FPGA/ASIC design flow

    RTL sign-off can be:
    - From management point of view, it is the point of time on schedule that project manager put for design team to finish Verilog coding job. Usually it is deadline.
    - From design point of view, it is the event that designer close all necessary verification and confirm there is no more change in RTL, no more issue with synthesis.

    Sign-off always has a list of conditions. You need to complete it before saying "sign-off"

    There is no tool to do RTL sign-off by itself.
    To improve one's brain, the doors are needed over the keys.



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    Re: What is RTL Signoff in FPGA/ASIC design flow

    OK...I came across a commercial tool (Synopsys Spyglass link here ). First of all, is this a well known RTL sign off tool. Also it has several components such as Linting, clock domain verification, reset verification, DFT analysis etc. Are these standard steps before RTL sign off/ am I missing something important?

    Thanks,
    Hobbyiclearner



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    Re: What is RTL Signoff in FPGA/ASIC design flow

    linting is the same as HAL, previously mentioned here. It is not mandatory, but it helps to catch some nasty behavior sometimes.
    CDC is a different problem, and is not necessarily resolved at RTL level.

    A tool like spyglass is more a project manager than a development tool. It is useful, but it doesn't set the industry standard for RTL freezing. It's too project dependent, company dependent, etc.



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    Re: What is RTL Signoff in FPGA/ASIC design flow

    OK... two queries... what is HAL (full form) and any free tools for that. What are the leading industry tools for RTL freezing pls.

    Thanks,
    Hobbyiclearner.



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    Re: What is RTL Signoff in FPGA/ASIC design flow

    Quote Originally Posted by hobbyiclearner View Post
    OK...I came across a commercial tool (Synopsys Spyglass link here ). First of all, is this a well known RTL sign off tool. Also it has several components such as Linting, clock domain verification, reset verification, DFT analysis etc. Are these standard steps before RTL sign off/ am I missing something important?

    Thanks,
    Hobbyiclearner
    Spyglass is a Tool to help checking Verilog coding styles, as you already listed them up.
    It can not help checking Verilog functions obviously.

    So, I can say that Spyglass checking is one item that can be listed in the Sign-off checklist.

    Moreover, it is depended on How you consider a Sign-off's meaning ?
    If you only need the Verilog code to get Pass with Spyglass then you will release it to other guys, you can called Spyglass is your Sign-Off tool.
    To improve one's brain, the doors are needed over the keys.



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    Re: What is RTL Signoff in FPGA/ASIC design flow

    ThisIsNoTSpam wrote:
    linting is the same as HAL, previously mentioned here.
    Well the process is know as Lint checks and HAL is a tool from Cadence to do the Lint Check to be precise.

    any free tools for that
    I don't think there are free tools for Lint checks (write a good RTL, if you don't have money or the tools ).

    What are the leading industry tools for RTL freezing pls.
    In my opinion Spyglass is the best. Next can be Cadence HAL (Cadence EDA tools are cheaper and more widely used...). Have used both, Spyglass is much better than HAL.
    FPGA enthusiast!



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    Re: What is RTL Signoff in FPGA/ASIC design flow

    I still think OP is confusing sign-off with lots of things. Linting and sign-off are not the same. Sign-off would be often used to described a piece of logic that was verified thoroughly and it is ready for implementation.



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    Re: What is RTL Signoff in FPGA/ASIC design flow

    Correct!
    Linting checks & sign-off is not the same.

    Actually up to #4 the question asked in #1 was ANSWERED.
    In my opinion the OP either got confused and/or has deviated from the topic.

    This is why it is always stressed in this forum to create different threads for individual topics, but the newer members rarely follow it.
    FPGA enthusiast!



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    Re: What is RTL Signoff in FPGA/ASIC design flow

    Linting can be a step in a sign-off process that may include many more things like simulation, synthesis warning checks, as stated earlier it's the final step that says: "I'm done with the code, we can start having it laid out with the back end tools."

    The reason for having such a step is due to the cost in both time and actual money of changing things after the back end flow has started (not as much of a problem with FPGAs).

    e.g. if you didn't simulate a major function, but claimed the design was done, then later wrote a testcase to verify that portion of the design after your "sign-off" and after the fab received the taped-out design and created masks for it....$$$$$$ wasted (with you placed on the next layoff list or fired outright).



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