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[SOLVED] Testability Measurement Tools

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guru2kiot

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Is there any testability measurement tool available for podem or D-algorithms???please can anyone tell me what are tools for testability measurement ???
 

I am not familiar with the term testability measurament. Care to elaborate? Maybe you meant test coverage?
 
thanks for your reply....

yes,testability measurement means that for calculate test coverage and also Controllability,observability measures & estimation of test vector length.......
 
thanks for your reply....

yes,testability measurement means that for calculate test coverage and also Controllability,observability measures & estimation of test vector length.......

all the major EDA companies have some tool that will do that for you. you can even do some analysis inside the synthesis tool to improve the observability if you want to.
 

thanks for your valuable suggestion....
I am asking what are the tools used to calculate the fault coverage,Controllability,observability measurements & estimation of test vector length???
please can anyone tell me what are tools for testability measurements ???
 
If I have understood correctly, you are looking for ATPG (Automatic Test pattern Generation) tools.
Cadence Encounter.
Synopsys TetraMax.

You have to generate different test-patterns to check various faults.
 
Thank you for your reply....
no, generating test patterns for various faults is one of my idea... my another idea is using various faults to calculate the fault coverage,point of Controllability,point of observability measurements & estimation of test vector length....
So that i need a testability measurement tool...please can anyone tell me the suggestion what are tools available for 'testability measurements' ??
 
using various faults to calculate the fault coverage,point of Controllability,point of observability measurements & estimation of test vector length....
Your answer is confusing to me!

Do you aim to perform "testability measurement" for a synthesized design *before* the insertion of scan chains?

Because once scan-chains are inserted, then it is easier to test faults using industry standard ATPG tools.
 
if i confusing you means really sorry........

yes my aim is to perform testability measurement by using particular circuit netlist(gate level),then by applying various faults to the circuit & apply ATPG algorithms...then we can get testability measurements like fault coverage test vector length..so thats why i asked about testability measurement tools......
 
I think we are missing something here....there are industry standard flows. So let's refer to that to disperse the cloud of doubt.

See slide.page nos.-10 here: https://www.eng.auburn.edu/~strouce/class/elec6970/NelsonBIST.pdf

Now tell me which part you are talking about?

Also please consider my Q again in #8:
Do you aim to perform "testability measurement" for a synthesized design *before* the insertion of scan chains?
 
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all the major EDA companies have some tool that will do that for you. you can even do some analysis inside the synthesis tool to improve the observability if you want to.

this is getting more and more confusing so I will quote myself as that was already the right answer.

all vendors offer tools that will do what you want, whatever it is that you want. you want coverage? they will give. you want test vector length? they will give.

it seems like you have never used any of these tools. they do exist and are used on a daily basis. do you have access to cadence or mentor or synopsys tools at your institution?
 
If i made any confusions means sorry to all
i am not used any standard tools so far.....in future days i am going to access standard tools through institution.....before that my plan is searching any other testability measurement tool......through google search today i found one tool for testability measurement..............if i confused means once again sorry.....thankyou very much (dpaul & ThisIsNotSam) your valuable responses here.......
 

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