fakourm
Newbie level 3
hi every body
i am working in drf1101 that it uses cc1101 for transiver . i can read and write its registers. but sometime the registers dont set currectly and i have confused.
also i cant send or recieve any data.
i use a board that design it by myself.
this is my code for transfer side
help me please:sad:
i am working in drf1101 that it uses cc1101 for transiver . i can read and write its registers. but sometime the registers dont set currectly and i have confused.
also i cant send or recieve any data.
i use a board that design it by myself.
this is my code for transfer side
Code:
/*
* transiver mega2560-cc1101-test.c
*
* Created: 10/01/2016 04:05:24 ب.ظ
* Author : Ramin
*/
#define F_CPU 16000000UL
#include <avr/io.h>
#include <util/delay.h>
//---------------------------------------
#define SCK_PORT PB1 // PORTB1
#define MISO_PIN PINB3 // PINB3
#define MOSI_PORT PB2 // PORTB2
#define SS_PORT PB5 // PORTB5
#define GDO0_PIN PINB7 // PINB7
#define GDO2_PIN PINB6 // PINB6
//----------------------------------------
//***************************************CC1101 define**************************************************//
// CC1101 CONFIG REGSITER
#define CC1101_IOCFG2 0x00 // GDO2 output pin configuration
#define CC1101_IOCFG1 0x01 // GDO1 output pin configuration
#define CC1101_IOCFG0 0x02 // GDO0 output pin configuration
#define CC1101_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
#define CC1101_SYNC1 0x04 // Sync word, high INT8U
#define CC1101_SYNC0 0x05 // Sync word, low INT8U
#define CC1101_PKTLEN 0x06 // Packet length
#define CC1101_PKTCTRL1 0x07 // Packet automation control
#define CC1101_PKTCTRL0 0x08 // Packet automation control
#define CC1101_ADDR 0x09 // Device address
#define CC1101_CHANNR 0x0A // Channel number
#define CC1101_FSCTRL1 0x0B // Frequency synthesizer control
#define CC1101_FSCTRL0 0x0C // Frequency synthesizer control
#define CC1101_FREQ2 0x0D // Frequency control word, high INT8U
#define CC1101_FREQ1 0x0E // Frequency control word, middle INT8U
#define CC1101_FREQ0 0x0F // Frequency control word, low INT8U
#define CC1101_MDMCFG4 0x10 // Modem configuration
#define CC1101_MDMCFG3 0x11 // Modem configuration
#define CC1101_MDMCFG2 0x12 // Modem configuration
#define CC1101_MDMCFG1 0x13 // Modem configuration
#define CC1101_MDMCFG0 0x14 // Modem configuration
#define CC1101_DEVIATN 0x15 // Modem deviation setting
#define CC1101_MCSM2 0x16 // Main Radio Control State Machine configuration
#define CC1101_MCSM1 0x17 // Main Radio Control State Machine configuration
#define CC1101_MCSM0 0x18 // Main Radio Control State Machine configuration
#define CC1101_FOCCFG 0x19 // Frequency Offset Compensation configuration
#define CC1101_BSCFG 0x1A // Bit Synchronization configuration
#define CC1101_AGCCTRL2 0x1B // AGC control
#define CC1101_AGCCTRL1 0x1C // AGC control
#define CC1101_AGCCTRL0 0x1D // AGC control
#define CC1101_WOREVT1 0x1E // High INT8U Event 0 timeout
#define CC1101_WOREVT0 0x1F // Low INT8U Event 0 timeout
#define CC1101_WORCTRL 0x20 // Wake On Radio control
#define CC1101_FREND1 0x21 // Front end RX configuration
#define CC1101_FREND0 0x22 // Front end TX configuration
#define CC1101_FSCAL3 0x23 // Frequency synthesizer calibration
#define CC1101_FSCAL2 0x24 // Frequency synthesizer calibration
#define CC1101_FSCAL1 0x25 // Frequency synthesizer calibration
#define CC1101_FSCAL0 0x26 // Frequency synthesizer calibration
#define CC1101_RCCTRL1 0x27 // RC oscillator configuration
#define CC1101_RCCTRL0 0x28 // RC oscillator configuration
#define CC1101_FSTEST 0x29 // Frequency synthesizer calibration control
#define CC1101_PTEST 0x2A // Production test
#define CC1101_AGCTEST 0x2B // AGC test
#define CC1101_TEST2 0x2C // Various test settings
#define CC1101_TEST1 0x2D // Various test settings
#define CC1101_TEST0 0x2E // Various test settings
//----------------------------------------
#define WRITE_BURST 0x40 //
#define READ_SINGLE 0x80 // IN CC1101
#define READ_BURST 0xC0 //
#define BYTES_IN_RXFIFO 0x7F //
//-----------------------------------------
//CC1101 Strobe commands
//CC1101 Strobe commands
#define CC1101_SRES 0x30 // Reset chip.
#define CC1101_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
// If in RX/TX: Go to a wait state where only the synthesizer is
// running (for quick RX / TX turnaround).
#define CC1101_SXOFF 0x32 // Turn off crystal oscillator.
#define CC1101_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
// (enables quick start).
#define CC1101_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
// MCSM0.FS_AUTOCAL=1.
#define CC1101_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
// MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled:
// Only go to TX if channel is clear.
#define CC1101_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
// Wake-On-Radio mode if applicable.
#define CC1101_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
#define CC1101_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
#define CC1101_SPWD 0x39 // Enter power down mode when CSn goes high.
#define CC1101_SFRX 0x3A // Flush the RX FIFO buffer.
#define CC1101_SFTX 0x3B // Flush the TX FIFO buffer.
#define CC1101_SWORRST 0x3C // Reset real time clock.
#define CC1101_SNOP 0x3D // No operation. May be used to pad strobe commands to two
// INT8Us for simpler software.
//CC1101 STATUS REGSITER
#define CC1101_PARTNUM 0x30
#define CC1101_VERSION 0x31
#define CC1101_FREQEST 0x32
#define CC1101_LQI 0x33
#define CC1101_RSSI 0x34
#define CC1101_MARCSTATE 0x35
#define CC1101_WORTIME1 0x36
#define CC1101_WORTIME0 0x37
#define CC1101_PKTSTATUS 0x38
#define CC1101_VCO_VC_DAC 0x39
#define CC1101_TXBYTES 0x3A
#define CC1101_RXBYTES 0x3B
//CC1101 PATABLE,TXFIFO,RXFIFO
#define CC1101_PATABLE 0x3E
#define CC1101_TXFIFO 0x3F
#define CC1101_RXFIFO 0x3F
//----------------------------------------
#define WRITE_BURST 0x40 //
#define READ_SINGLE 0x80 // IN CC1101
#define READ_BURST 0xC0 //
#define BYTES_IN_RXFIFO 0x7F //
//-----------------------------------------
unsigned char txBuffer[] = {0x04,0x5b,0x25,4,5};
unsigned char rxBuffer[61]; // Length unsigned char + 2 status unsigned chars are not stored in this buffer
unsigned char in1=0,in2=0,in3=0,in4,in5,in6,in7,in8,in9,in10,in11aMARCSTATE,in12,in13,in14,timout,size1,d1,d2,i; // FOR TESTING
void SpiInit(void)
{ // SCK MOSI MISO CS GDO2 GDO0
DDRB = (1<<DDB0)|(1<<DDB1)|(1<<DDB2)|(0<<DDB3)|(1<<DDB5)|(0<<DDB6)|(0<<DDB7);
//Enable SPI master mode
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
unsigned char SpiTransfer(unsigned char Data)
{
SPDR = Data;
while(!(SPSR & (1<<SPIF)));
return SPDR;
}
void reset_CC1101(void)
{
PORTB &= ~(1<<SS_PORT);
_delay_ms(1);
PORTB |= 1<<SS_PORT;
_delay_ms(1);
PORTB &= ~(1<<SS_PORT);
while (PINB & (1<< MISO_PIN));
SpiTransfer(CC1101_SRES); // Reset chip.
PORTB |= 1<<SS_PORT;
}
void Init(void)
{
SpiInit();
PORTB = 1<<SS_PORT;
PORTB = 1<<SCK_PORT;
PORTB = 0<<MOSI_PORT;
reset_CC1101();
}
void SpiWriteReg(unsigned char addr, unsigned char data)
{
PORTB &= ~(1<<SS_PORT);
while (PINB & (1<< MISO_PIN));
SpiTransfer(addr);
SpiTransfer(data);
PORTB |= 1<<SS_PORT;
}
void SpiWriteBurstReg(unsigned char addr,unsigned char *buffer, unsigned char size)
{
unsigned char i, temp;
temp = addr | WRITE_BURST;
PORTB &= ~(1<<SS_PORT);
while (PINB & (1<< MISO_PIN));
SpiTransfer(temp);
for(i=0;i<size;i++)
{
SpiTransfer(buffer[i]);
}
PORTB |= 1<<SS_PORT;
}
void SpiStrobe(unsigned char strobe)
{
PORTB &= ~(1<<SS_PORT);
while (PINB & (1<< MISO_PIN));
SpiTransfer(strobe);
PORTB |= 1<<SS_PORT;
}
unsigned char SpiReadReg(unsigned char addr)
{
unsigned char temp, data;
// changed status_register
temp = addr|READ_SINGLE;
PORTB &= ~(1<<SS_PORT);
while (PINB & (1<< MISO_PIN));
SpiTransfer(temp);
data = SpiTransfer(0);
PORTB |= 1<<SS_PORT;
return data;
}
void SpiReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char size)
{
unsigned char i, temp;
temp = addr|READ_BURST;
PORTB &= ~(1<<SS_PORT);
while (PINB & (1<< MISO_PIN));
SpiTransfer(temp);
for(i=0;i<size;i++)
{
buffer[i] = SpiTransfer(0);
}
PORTB |= 1<<SS_PORT;
}
unsigned char SpiReadStatus(unsigned char addr)
{
unsigned char data, temp;
temp = addr|READ_BURST;
PORTB &= ~(1<<SS_PORT);
while (PINB & (1<< MISO_PIN));
SpiTransfer(temp);
data = SpiTransfer(0);
PORTB |= 1<<SS_PORT;
return data;
}
void SendData(unsigned char *txBuffer, unsigned char size)
{
SpiWriteReg(CC1101_TXFIFO,size);
SpiWriteBurstReg(CC1101_TXFIFO,txBuffer,size);
SpiStrobe(CC1101_STX);
while(!(PINB & (1<< GDO0_PIN)));
while(PINB & (1<< GDO0_PIN));
SpiStrobe(CC1101_SFTX);
}
unsigned char ReceiveData(unsigned char *rxBuffer)
{
unsigned char size, status[2];
SpiStrobe(CC1101_SRX);
while(!(PINB & (1<< GDO0_PIN)));
while(PINB & (1<< GDO0_PIN));
if(SpiReadStatus(CC1101_RXBYTES) & BYTES_IN_RXFIFO)
{
size = SpiReadReg(CC1101_RXFIFO);
SpiReadBurstReg(CC1101_RXFIFO,rxBuffer,size);
SpiReadBurstReg(CC1101_RXFIFO,status,2);
SpiStrobe(CC1101_SIDLE);
SpiStrobe(CC1101_SFRX);
return size;
}
else
{
SpiStrobe(CC1101_SIDLE);
SpiStrobe(CC1101_SFRX);
return 0;
}
}
void RegConfigSettings1(void)
{
SpiWriteReg(CC1101_FSCTRL1,0x0C);
SpiWriteReg(CC1101_FSCTRL0,0x00);
SpiWriteReg(CC1101_FREQ2,0x10);
SpiWriteReg(CC1101_FREQ1,0xA7);
SpiWriteReg(CC1101_FREQ0,0x62);
SpiWriteReg(CC1101_MDMCFG4,0x2D);
SpiWriteReg(CC1101_MDMCFG3,0x3B);
SpiWriteReg(CC1101_MDMCFG2,0x13);
SpiWriteReg(CC1101_MDMCFG1,0x22);
SpiWriteReg(CC1101_MDMCFG0,0xF8);
SpiWriteReg(CC1101_CHANNR,0x00);
SpiWriteReg(CC1101_DEVIATN,0x62);
SpiWriteReg(CC1101_FREND1, 0xB6);
SpiWriteReg(CC1101_FREND0, 0x10);
SpiWriteReg(CC1101_MCSM0 , 0x18);
SpiWriteReg(CC1101_FIFOTHR , 0x07);
SpiWriteReg(CC1101_FOCCFG, 0x1D);
SpiWriteReg(CC1101_BSCFG, 0x1C);
SpiWriteReg(CC1101_AGCCTRL2, 0xC7);
SpiWriteReg(CC1101_AGCCTRL1, 0x00);
SpiWriteReg(CC1101_AGCCTRL0, 0xB0);
SpiWriteReg(CC1101_FSCAL3, 0xEA);
SpiWriteReg(CC1101_FSCAL2, 0x2A);
SpiWriteReg(CC1101_FSCAL1, 0x00);
SpiWriteReg(CC1101_FSCAL0, 0x1F);
SpiWriteReg(CC1101_FSTEST, 0x59);
SpiWriteReg(CC1101_TEST2, 0x88);
SpiWriteReg(CC1101_TEST1, 0x31);
SpiWriteReg(CC1101_TEST0, 0x09);
SpiWriteReg(CC1101_IOCFG2, 0x29); //serial clock.synchronous to the data in synchronous serial mode
SpiWriteReg(CC1101_IOCFG0, 0x06); //asserts when sync word has been sent/received, and de-asserts at the end of the packet
SpiWriteReg(CC1101_PKTCTRL1, 0x04); //two status unsigned chars will be appended to the payload of the packet,including RSSI LQI and CRC OK
//No address check
SpiWriteReg(CC1101_PKTCTRL0, 0x05); //whitening off;CRC Enable£»variable length packets, packet length configured by the first unsigned char after sync word
SpiWriteReg(CC1101_ADDR,0x00); //address used for packet filtration.
SpiWriteReg(CC1101_PKTLEN, 0xFF); //61 unsigned chars max length
}
void RegConfigSettings2(void)
{
SpiWriteReg(CC1101_FSCTRL1,0x08);
SpiWriteReg(CC1101_FSCTRL0,0x00);
SpiWriteReg(CC1101_FREQ2,0x10);
SpiWriteReg(CC1101_FREQ1,0xA7);
SpiWriteReg(CC1101_FREQ0,0x62);
SpiWriteReg(CC1101_MDMCFG4,0x5B);
SpiWriteReg(CC1101_MDMCFG3,0xF8);
SpiWriteReg(CC1101_MDMCFG2,0x03);
SpiWriteReg(CC1101_MDMCFG1,0x22);
SpiWriteReg(CC1101_MDMCFG0,0xF8);
SpiWriteReg(CC1101_CHANNR,0x00);
SpiWriteReg(CC1101_DEVIATN,0x47);
SpiWriteReg(CC1101_FREND1, 0xB6);
SpiWriteReg(CC1101_FREND0, 0x10);
SpiWriteReg(CC1101_MCSM0 , 0x18);
SpiWriteReg(CC1101_FOCCFG, 0x1D);
SpiWriteReg(CC1101_BSCFG, 0x1C);
SpiWriteReg(CC1101_AGCCTRL2, 0xC7);
SpiWriteReg(CC1101_AGCCTRL1, 0x00);
SpiWriteReg(CC1101_AGCCTRL0, 0xB2);
SpiWriteReg(CC1101_FSCAL3, 0xEA);
SpiWriteReg(CC1101_FSCAL2, 0x2A);
SpiWriteReg(CC1101_FSCAL1, 0x00);
SpiWriteReg(CC1101_FSCAL0, 0x11);
SpiWriteReg(CC1101_FSTEST, 0x59);
SpiWriteReg(CC1101_TEST2, 0x81);
SpiWriteReg(CC1101_TEST1, 0x35);
SpiWriteReg(CC1101_TEST0, 0x09);
SpiWriteReg(CC1101_IOCFG2, 0x0B); //serial clock.synchronous to the data in synchronous serial mode
SpiWriteReg(CC1101_IOCFG0, 0x06); //asserts when sync word has been sent/received, and de-asserts at the end of the packet
SpiWriteReg(CC1101_PKTCTRL1, 0x04); //two status unsigned chars will be appended to the payload of the packet,including RSSI LQI and CRC OK
//No address check
SpiWriteReg(CC1101_PKTCTRL0, 0x05); //whitening off;CRC Enable£»variable length packets, packet length configured by the first unsigned char after sync word
SpiWriteReg(CC1101_ADDR,0x00); //address used for packet filtration.
SpiWriteReg(CC1101_PKTLEN, 0x3D); //61 unsigned chars max length
}
void RegConfigSettings3(void)
{
SpiWriteReg(CC1101_IOCFG0 ,0x06);
SpiWriteReg(CC1101_FIFOTHR ,0x47);
SpiWriteReg(CC1101_PKTCTRL0,0x05);
SpiWriteReg(CC1101_FSCTRL1 ,0x06);
SpiWriteReg(CC1101_FREQ2 ,0x10);
SpiWriteReg(CC1101_FREQ1 ,0xB1);
SpiWriteReg(CC1101_FREQ0 ,0x3B);
SpiWriteReg(CC1101_MDMCFG4 ,0xFE);
SpiWriteReg(CC1101_MDMCFG3 ,0x43);
SpiWriteReg(CC1101_MDMCFG2 ,0x1B);
SpiWriteReg(CC1101_DEVIATN ,0x15);
SpiWriteReg(CC1101_MCSM0 ,0x18);
SpiWriteReg(CC1101_FOCCFG ,0x16);
SpiWriteReg(CC1101_WORCTRL ,0xFB);
SpiWriteReg(CC1101_FSCAL3 ,0xEA);
SpiWriteReg(CC1101_FSCAL2 ,0x2A);
SpiWriteReg(CC1101_FSCAL1 ,0x00);
SpiWriteReg(CC1101_FSCAL0 ,0x1F);
SpiWriteReg(CC1101_TEST2 ,0x81);
SpiWriteReg(CC1101_TEST1 ,0x35);
SpiWriteReg(CC1101_TEST0 ,0x09);
}
void RegConfigSettings4(void)
{
SpiWriteReg(CC1101_IOCFG2,0x29); //serial clock.synchronous to the data in synchronous serial mode
SpiWriteReg(CC1101_IOCFG1,0x2e);
SpiWriteReg(CC1101_IOCFG0,0x06); //asserts when sync word has been sent/received, and de-asserts at the end of the packet
SpiWriteReg(CC1101_FIFOTHR,0x47);
SpiWriteReg(CC1101_SYNC1,0xd3);
SpiWriteReg(CC1101_SYNC0,0x91);
SpiWriteReg(CC1101_PKTLEN, 0x3D); //61 unsigned chars max length
SpiWriteReg(CC1101_PKTCTRL1, 0x04); //two status unsigned chars will be appended to the payload of the packet,including RSSI LQI and CRC OK
//no address check
SpiWriteReg(CC1101_PKTCTRL0, 0x05); //whitening off;CRC Enable£»variable length packets, packet length configured by the first unsigned char after sync word
SpiWriteReg(CC1101_ADDR,0x00); //address used for packet filtration.
SpiWriteReg(CC1101_CHANNR,0x00);
SpiWriteReg(CC1101_FSCTRL1,0x06);
SpiWriteReg(CC1101_FSCTRL0,0x00);
SpiWriteReg(CC1101_FREQ2,0x10);
SpiWriteReg(CC1101_FREQ1,0xb1);
SpiWriteReg(CC1101_FREQ0,0x3a);
SpiWriteReg(CC1101_MDMCFG4,0xf5);
SpiWriteReg(CC1101_MDMCFG3,0x83);
SpiWriteReg(CC1101_MDMCFG2,0x13);
SpiWriteReg(CC1101_MDMCFG1,0x22);
SpiWriteReg(CC1101_MDMCFG0,0xF8);
SpiWriteReg(CC1101_DEVIATN,0x15);
SpiWriteReg(CC1101_MCSM2 , 0x07);
SpiWriteReg(CC1101_MCSM1 , 0x3f);
SpiWriteReg(CC1101_MCSM0 , 0x18);
SpiWriteReg(CC1101_FOCCFG, 0x16);
SpiWriteReg(CC1101_BSCFG, 0x1C);
SpiWriteReg(CC1101_AGCCTRL2, 0xC7);
SpiWriteReg(CC1101_AGCCTRL1, 0x00);
SpiWriteReg(CC1101_AGCCTRL0, 0xB0);
SpiWriteReg(CC1101_WOREVT1, 0x87);
SpiWriteReg(CC1101_WOREVT0, 0x6b);
SpiWriteReg(CC1101_WORCTRL, 0xfb);
SpiWriteReg(CC1101_FREND1, 0xB6);
SpiWriteReg(CC1101_FREND0, 0x10);
SpiWriteReg(CC1101_FSCAL3, 0xE9);
SpiWriteReg(CC1101_FSCAL2, 0x2A);
SpiWriteReg(CC1101_FSCAL1, 0x00);
SpiWriteReg(CC1101_FSCAL0, 0x1f);
SpiWriteReg(CC1101_RCCTRL1, 0x41);
SpiWriteReg(CC1101_RCCTRL0, 0x00);
SpiWriteReg(CC1101_FSTEST, 0x59);
SpiWriteReg(CC1101_PTEST, 0x7f);
SpiWriteReg(CC1101_AGCTEST, 0x3f);
SpiWriteReg(CC1101_TEST2, 0x81);
SpiWriteReg(CC1101_TEST1, 0x35);
SpiWriteReg(CC1101_TEST0, 0x09);
SpiWriteReg(CC1101_PATABLE, 0xc8);
}
int main(void)
{
DDRE = 1<<DDE0;
PORTE |=1<<PE1;
Init();
RegConfigSettings4(); // setting
while (1)
{
in1 = SpiReadReg(CC1101_IOCFG0); // 06
in2 = SpiReadReg(CC1101_PKTLEN); // 3d
in3 = SpiReadReg(CC1101_MDMCFG4);//f5
in4 = SpiReadReg(CC1101_FSCAL2); //2a
in5 = SpiReadReg(CC1101_MDMCFG2); //13
in6 = SpiReadReg(CC1101_FREQ1); //b1
in7 = SpiReadReg(CC1101_DEVIATN); //15
in8 = SpiReadReg(CC1101_AGCCTRL2); //c7 //these codes are for testing
in9 = SpiReadReg(CC1101_FREQ2); //10
in10 = SpiReadReg(CC1101_AGCCTRL0); //b0
in11aMARCSTATE = SpiReadStatus(CC1101_MARCSTATE);
in12 = SpiReadReg(CC1101_TEST1); //35
in13 = SpiReadReg(CC1101_TEST2); //81
in14 = SpiReadReg(CC1101_FSCAL0); //1f
timout = SpiReadReg(CC1101_MCSM2); //07
d1=SpiReadStatus(CC1101_TXBYTES);
if (!(PINE & (1<< PINE1)))
{
_delay_ms(30);
in3=SpiReadStatus(CC1101_TXBYTES); // txbytes is 6 bytes
if (!(PINE & (1<< PINE1)) && in3 ==6 )
{
_delay_ms(1500);
PORTE |= 1<< PE0;
_delay_ms(1500);
PORTE &= ~(1<<PE0);
SpiStrobe(CC1101_STX);
while(!(PINB & (1<< GDO0_PIN))); // for sync bytes
while(PINB & (1<< GDO0_PIN)); // for data that it is sent
while(!(PINE & (1<< PINE1))); // for button
in11aMARCSTATE=SpiReadStatus(CC1101_MARCSTATE);
in2=SpiReadStatus(CC1101_TXBYTES); // length of tx buffer
SpiStrobe(CC1101_SFTX);
}
}
if ((in11aMARCSTATE==0x13||in11aMARCSTATE==0x0D)&& in2==6 )
{
for (i==0;i<=50;i++)
{
_delay_ms(80);
PORTE |= 1<< PE0;
_delay_ms(80);
PORTE &= ~(1<<PE0);
}
}
}
}help me please:sad:
)))))