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For example, a mobility reduction due to carrier velocity saturation starts at electric fields higher than so called critical field equal to 0.8 MV/m and 1.95 MV/m for electrons and holes respectively. It means that for given channel length like 100nm it becomes important for Vds (or Vdsat for mosfets working in penthode region) higher than ca 80 or 195 mV. Similar DIBL is related with so called characteristic length varied with process but related also to Vds voltage.
Also, some SCE like mobility degradation caused by vertical field is related to gate oxide thickness so increasing channel length doesn't help with this.
For example, a mobility reduction due to carrier velocity saturation starts at electric fields higher than so called critical field equal to 0.8 MV/m and 1.95 MV/m for electrons and holes respectively. It means that for given channel length like 100nm it becomes important for Vds (or Vdsat for mosfets working in penthode region) higher than ca 80 or 195 mV. Similar DIBL is related with so called characteristic length varied with process but related also to Vds voltage.
Also, some SCE like mobility degradation caused by vertical field is related to gate oxide thickness so increasing channel length doesn't help with this.
yeah. i read about those in the razavi. one of my homework ask me to find a length that SCE will not be a problem with the mos. so should i use SPICE to set the sweep of length v.s what kind of parameter so that i can find a length that will no cause SCE？
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