Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] asynchronous counter for testing

Status
Not open for further replies.
guru2kiot

guru2kiot

Junior Member level 2
Joined
Sep 2, 2016
Messages
22
Helped
8
Reputation
40
Reaction score
20
Trophy points
1,283
Activity points
1,444
is it possible to generate test pattern generation for asynchronous counter????
 

Why would you design an asynchronous counter in an FPGA!? That is not recommended under any circumstance.
 

If you do against all reason, writing a test bench shouldn't be the problem.
 
Theoretically it is possible to write a testbench for any hardware DUT. You have to make sure that the TB drives all the DUT inputs (in all possible combinations) and in parallel the TB monitors the DUT outputs.
 
yes Theoretically it is possible to do...but its difficult to implement and generate test patterns..
 
If you know how to write a test bench for a synchronous counter, it shouldn't be difficult. If not, start learning the basics.
 
ok.now i am understand... thank you very much for ur valuable response....i have another doubt how to apply the d-algorithm based concepts for asynchronous circuits using verilog????
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top