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    35 nm layout challenges

    Hi i did my layout design for 180nm. Scaling down technologies has effects included in it. Apart from just reduction of channel length, matching the circuit blocks, adding dummies what are the some of the other effects to be taken into account. i know some of effects like WPE, EM, IR and ESD. But what else. Can anyone please help??

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    Re: 35 nm layout challenges

    LWR, LER, boneheads, etc.
    Look on articles in IEEE Trans. on Electron Devices and Electron Devices Letters, and Solid State Electronics from ScienceDirect. There are a lot of articles threating about new or more important effects in nano-processes.



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    Re: 35 nm layout challenges

    layout dependent effects are a pain in the ass.



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    Re: 35 nm layout challenges

    thank you for the reply!!! Much appreciated. But i also have one more question to ask. So for 35nm i get to know some of the effects (as mentioned). Now i also want to learn about 28nm which is even further scaled down. how can i find the effects that actually affect a 28nm tech (apart from articles and papers on the site). Meaning generally when scaling what are the usual aspects that are looked for in transistor that we determine the effects. Like is this a job of the physical design engineers or engineers who deal with actual physics of that device who determine these effects??? Becoz i guess based on the physical device constraint of the scaling tech, a layout engineer does the layout accordingly. Or is a layout engineer actually also responsible to determine the possible effects. Becoz learning about an existing effect and actually determining an effect are different right.. Also then i suppose lot of R and D would come in play then.. I hope i am clear with the question. Can anyone kindly let me know please.. Thanks a lot!!! :)
    Last edited by preethi19; 13th September 2016 at 05:08.



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    Re: 35 nm layout challenges

    each technology brings something new, there is no rule of thumb. sometimes a material is modified and it changes everything (think high-K oxide), sometimes the transistor structure is changed completely (think finfets), sometimes the litho changes (think douple/triple patterning, LELE, etc).


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    Re: 35 nm layout challenges

    Thank you for the reply!!! Yes finfet are totally new structures. But say from 35nm to 28nm (both in CMOS), the only change in technology is the dimensions(scaling) right. So in this case we dont have to see the effects of different physical structure like that of finfets. So based on only dimensional scaling what are like the usual effects that people normally look for???



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