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    set up and hold fixing in FPGA

    In the case of ASIC, there are many ways to fix set up and hold like upsizing/downsizing cells, buffering/removing buffer, skew insertion, LVT/HVT cells etc. What about FPGA? I see many articles referring to fixing setup and hold violations in ASIC. But I don't see much help for FPGA. How can I deal with setup and hold violations in FPGA??

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    Re: set up and hold fixing in FPGA

    Quote Originally Posted by biju4u90 View Post
    But I don't see much help for FPGA. How can I deal with setup and hold violations in FPGA??
    Setup: Reduce the amount of logic before re-registering in a flip flop. In a word, pipelining.
    Hold: In a synchronous FPGA design, this will not happen. Stop using internally generated clocks and your hold time violations disappear.

    Kevin Jennings



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    Re: set up and hold fixing in FPGA

    Setup: Reduce the amount of logic before re-registering in a flip flop. In a word, pipelining.
    Pipelining is done in RTL level, right?? Is there any method in FPGA by which we can fix the set up and hold violations without altering our HDL code? In the case of ASIC, we can do this by resizing the cells or swapping the cells at synthesis level or by useful skew insertion at post CTS stage. Do we have any such methods in the case of FPGA??

    Hold: In a synchronous FPGA design, this will not happen. Stop using internally generated clocks and your hold time violations disappear.
    So that means hold violations won't occur if we are using a single clock domain for our whole design??



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    Re: set up and hold fixing in FPGA

    Quote Originally Posted by biju4u90 View Post
    Pipelining is done in RTL level, right??
    Yes
    Is there any method in FPGA by which we can fix the set up and hold violations without altering our HDL code?
    Yes, the synthesis tool has options for how hard it will work in order to improve timing; random number seeds that affect the fitter; design space explorers that iterate on various synthesis parameters in order to find something that works. Things like that. Peruse the synthesis tool documentation since the options are all very tool specific in how to use.

    In the case of ASIC, we can do this by resizing the cells or swapping the cells at synthesis level or by useful skew insertion at post CTS stage. Do we have any such methods in the case of FPGA??
    No, because the FPGA is an already design complete ASIC. All that is being done during 'FPGA design' is figuring out the contents of lookup tables, which transistors get enabled/disabled in order for signals to get from point A to point B, things like that. The actual hardware inside isn't changing, it's either being used or not. The 'higher drive / low skew' drivers are already located, the content of the RTL causes them to be used or not used as decided upon by the synthesis tool (which does a pretty good job mostly).

    So that means hold violations won't occur if we are using a single clock domain for our whole design??
    Correct. All the FPGAs I've seen guarantee that any flip flop Q output can be sent to any D input of any other flip flop and the skew between the clock inputs of those flip flops will be small enough that a hold time violation cannot occur. But read the datasheet for the particular device that interests you to verify...surprises can happen.

    Kevin Jennings


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    Re: set up and hold fixing in FPGA

    Quote Originally Posted by K-J View Post
    Yes
    Yes, the synthesis tool has options for how hard it will work in order to improve timing; random number seeds that affect the fitter; design space explorers that iterate on various synthesis parameters in order to find something that works. Things like that. Peruse the synthesis tool documentation since the options are all very tool specific in how to use.
    There are other fitter options, like register retiming, that alow the fitter to break your logic up and move the registers around a bit in order to minimise logic between registers. For example, a mutliply accumulator followed by a shift register would allow the tool to move one of the pipeline stages of the shift reg between the multiply and accumulate function without modifying the rtl. Its not guaranteed and you cannot control it more that "on" or "off", but it might give you an edge in some tougher spots.

    If you then get really stuck, look into logic locking specific parts of your chip (ie. assinging specific entities to specific regions of a chip so that they have priority there) and ensure you have specified all false and multicycle paths in your SDC file. And as a final case, specify max delay constraints between particularly hard registers to make the fitter work extra hard on that specific path. But this really should be a last resort.

    By far the easiest thing to do is change the RTL.


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    Re: set up and hold fixing in FPGA

    Quote Originally Posted by TrickyDicky View Post
    There are other fitter options, like register retiming, that alow the fitter to break your logic up and move the registers around a bit in order to minimise logic between registers. For example, a mutliply accumulator followed by a shift register would allow the tool to move one of the pipeline stages of the shift reg between the multiply and accumulate function without modifying the rtl. Its not guaranteed and you cannot control it more that "on" or "off", but it might give you an edge in some tougher spots.

    If you then get really stuck, look into logic locking specific parts of your chip (ie. assinging specific entities to specific regions of a chip so that they have priority there) and ensure you have specified all false and multicycle paths in your SDC file. And as a final case, specify max delay constraints between particularly hard registers to make the fitter work extra hard on that specific path. But this really should be a last resort.

    By far the easiest thing to do is change the RTL.
    Bolded the part that matters the most. This is specially true if your violation paths are all coming from the same module/register/path in a systematic way.


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    Re: set up and hold fixing in FPGA

    In the past, I've only had non-io based hold violations when the tools gave up. Basically when a part of the build process stopped attempting to fix setup errors. The optimization efforts stopped. The design was then analyzed. Hold errors only occurred because no effort was made to correct them.

    The hold violations for my cases were on hard-IP.



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    Re: set up and hold fixing in FPGA

    An excerpt from TrickyDicky's post in #5

    If you then get really stuck, look into logic locking specific parts of your chip (ie. assinging specific entities to specific regions of a chip so that they have priority there) and ensure you have specified all false and multicycle paths in your SDC file. And as a final case, specify max delay constraints between particularly hard registers to make the fitter work extra hard on that specific path. But this really should be a last resort.
    Are IDDRs or ODDRs examples of hard registers in an FPGA (I have Xilinx Artix 7 in my mind)?



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    Re: set up and hold fixing in FPGA

    I really meant that the fitter was having a hard (difficult) time, rather than hard as in hard IP.
    I wasnt specifying any particular registers.

    Ive had experience using Altera's DSE and when you have single paths that fail consistently and you cannot change RTL, specify a false path or multicycle path, the final resort was to overconstrain that single path only in the fitter, so that it would make it more likely to pass timing at the real speed.

    Eg. For a 200 Mhz clock, set the max delay in the fitter to be 3ns, so it might actually meet 5ns when it comes to STA.



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    Re: set up and hold fixing in FPGA

    ok, I misunderstood. Thanks.



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