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I don't have Altera tools available, so I can't check.
1. If they encrypt their core...forget it you can't read them.
1.a. If you can generate a netlist of the encrypted core from synthesized RTL (don't know if Quartus can do this) then you might find the memory array in the netlist code.
2. If its an un-encrypted core then find the memory array (which is likely to be a variable assuming VHDL) and add an assignment to a signal to make it visible in simulation (it should already be visible in Verilog). Oh yeah, this will really slow simulation down depending on the size of the memory.
Afaik, they provide simulation models for their libraries, so you can just dig into their code to find the big array variable (its a shared variable iirc) in the memory instantiated inside the FIFO.
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