The guard rings for latchup prevention is opposite to guard rings for substrate noise

1)latchup prevention, To reduce disturbances from minority carrier, guard ring around noisy transistors can be used. Guard ring considerations are as following,
(i) NMOS in the p-substrate with should be surrounded by N-well guard ring.
N-well guard ring should be tied to VDD. The N-diffusions from the NMOS could inject stray electrons into the substrate. These stray electrons could be collected efficiently by the N-well guard ring that is biased to VDD to attract the electrons.
(ii) PMOS in the N-well should be surrounded with P-diffusion guard ring.
P-diffusion guard ring should be tied to ground. P-diffusions from the
PMOS inject stray holes into the N-well. These stray holes could be collected efficiently by the P-diffusion guard ring that is biased to ground to attract the holes.




2)To reduce substrate coupling noise, the guard ring may be used in the following configuration around critical transistors.
(i) Surround NMOS in the p-substrate with p-tap guard ring that is connected to ground.
(ii) Surround PMOS in the N-well with n-tap guard ring that is connected to VDD.

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my conclusion is these are two opposite mechanism, one is draw in, and the another is to repell.

The guard rings used for latchup prevention is to draw in the extra electrons for NMOS and extra holes for PMOS. Whereas the guards rings used in substrate noise reduction to repell extra electrons from NMOS away from guard ring therefore made the electrons stay inside and affect other areas in the substrate; Likewise for PMOS guard ring.

Is that correct?

There will be no "repulsion". Outside the depletion
regions the substrate is field-free.

Depletion regions are "sinks" for free minority carriers
because any that diffuse into the depletion field will
be swept to the appropriate contact.

Guardrings also improve shunting resistances which
is the main thing for latchup suppression. They also
by their presence increase width of and make higher-
doped any lateral BJT "base" region (e.g. N+ D, Psub,
Nwell at minum spacings is a much "hotter" lateral
NPN than N+ D, Psub, P+, Psub, Nwell (draw it out
for yourself and see).

dick_freebird said:

There will be no "repulsion". Outside the depletion
regions the substrate is field-free.
.

Click to expand...

why no repulsion? case 2
2)To reduce substrate coupling noise, the guard ring may be used in the following configuration around critical transistors.
(i) Surround NMOS in the p-substrate with p-tap guard ring that is connected to ground.


So you N-P-N, the majority carrier will be electrons. what 's purpose of guard ring connected to ground?
It cannot be attract those stray electrons right? The grounded guard ring should repell the stray electron, That's the purpose right?

The same-type guardring simply enforces a local
substrate potential that's equal to ground (as seen
in the interconnect). It may serve to recombine e-
that happen to diffuse into it (short lifetime) but has
no depletion region to pull electrons by drift. It also
makes sure the parasitic BJT has a well shunted base.

Counter-type, opposite-bias rings (or pairs) are more
effective in pulling minority carriers, their depletion
region is a larger and deeper "trap" for them.

dick_freebird said:

but has
no depletion region to pull electrons by drift. It also
makes sure the parasitic BJT has a well shunted base.

Counter-type, opposite-bias rings (or pairs) are more
effective in pulling minority carriers, their depletion
region is a larger and deeper "trap" for them.

Click to expand...

I don't understand your statement of "if depletetion region then drift cannot occur"

Isn't depletion formed by reverse bias?

If it's forward biased then there would little depletion region and drift can still happen.

You are making stuff up now and I can't respond to every
conjecture. Let alone things I haven't even said.