GhostInABox
Junior Member level 2
Hi all,
I realised that my approach to HDL development is very inefficient. I am still uncertain on how some of the constructs will be synthesized and have to go back and forth between the Synthesis tool ( VIVADO ) . But waiting for VIVADO or ISE to synthesise my design each time is painful.
I am wondering if anyone who is in an environment who has to write a lot of VHDL could share their approach to HDL development . I am guessing that most of its done in some editor ( Vi) and Synthesis tool used in command line OR is just the editor and Simulation tool, finally the synthesis tool will be run to see if its synthesizable.
I have at my disposal , Xilnx VIVADO , ISE and Modelsim in a Windows environment.
Any insights are much appreciated
I realised that my approach to HDL development is very inefficient. I am still uncertain on how some of the constructs will be synthesized and have to go back and forth between the Synthesis tool ( VIVADO ) . But waiting for VIVADO or ISE to synthesise my design each time is painful.
I am wondering if anyone who is in an environment who has to write a lot of VHDL could share their approach to HDL development . I am guessing that most of its done in some editor ( Vi) and Synthesis tool used in command line OR is just the editor and Simulation tool, finally the synthesis tool will be run to see if its synthesizable.
I have at my disposal , Xilnx VIVADO , ISE and Modelsim in a Windows environment.
Any insights are much appreciated