VHDL editor, synthesis tool and simulator for FPGA's

Hi all,

I realised that my approach to HDL development is very inefficient. I am still uncertain on how some of the constructs will be synthesized and have to go back and forth between the Synthesis tool ( VIVADO ) . But waiting for VIVADO or ISE to synthesise my design each time is painful.

I am wondering if anyone who is in an environment who has to write a lot of VHDL could share their approach to HDL development . I am guessing that most of its done in some editor ( Vi) and Synthesis tool used in command line OR is just the editor and Simulation tool, finally the synthesis tool will be run to see if its synthesizable.

I have at my disposal , Xilnx VIVADO , ISE and Modelsim in a Windows environment.

Any insights are much appreciated

It probably depends on the user. I do the vast majority of my coding in Vim, but do switch back to Vivado to do elaboration and synthesis. Modelsim for simulation.

Typically I start new code by doing many small synthesis runs that aren't actually intended to be full functional designs. Just enough to show approximate area/performance and to see what possible resource issues occur. As you learn what can be synthesized, the need to do synthesis to see if some code construct works will be reduced.

I also use vim heavily. you can get gvim in windows as well, but you have to fix parts of it. Some people like emacs, sublime, or notepad++. I couldn't get marker-based code-folding to work in Notepad++, so I don't use it for VHDL/Verilog.

If you use windows command line, remember that you can set the width of the terminal by right clicking on the title bar and selecting "properties". The layout tab has options for width and some other stuff.

Before I even start development, there is documentation to produce : architecture documents, detailed design and test plans. When these are written and reviewed, then you start writing code.
Most of my dev is done in Notepad++ and Modelsim. Synthesis is left until later (unless Im doing small synth tests like in #2 above). I just use modelsim transcript window mannually running commands/scripts or the command line.
But a lot of time is spent setting up scripts (we have a heavily scripted build farm environment) - our FPGAs often have 100s of hand written VHDL with many generated cores. Without scripts, maintaining them would be very tedious.