imbichie
Full Member level 6
Hi All,
I am using Virtex 7 1157 FPGA.
My design with RTL is freezes. I cannot modify a single line in the RTL.
I needs to infer the DSP blocks for particular adder logic in my design.
During the Synplify synthesis, I observed that automatically these adder are not using DSP blocks.
Is there any *.sdc constraints for inferring the DSP block for adders (also for XOR) logic in the design.
IN RTL i know by using the syn_multsyle will do this.
But RTL is freezes, so only option is the SDC file.
In vivado tool we have options for this :
I need the similar sdc constraints for synplify.
After the synplify I will be using vivado for place and route.
I am using Virtex 7 1157 FPGA.
My design with RTL is freezes. I cannot modify a single line in the RTL.
I needs to infer the DSP blocks for particular adder logic in my design.
During the Synplify synthesis, I observed that automatically these adder are not using DSP blocks.
Is there any *.sdc constraints for inferring the DSP block for adders (also for XOR) logic in the design.
IN RTL i know by using the syn_multsyle will do this.
But RTL is freezes, so only option is the SDC file.
In vivado tool we have options for this :
Code:
set_property use_dsp48 yes [get_cells <signal>]I need the similar sdc constraints for synplify.
After the synplify I will be using vivado for place and route.
Last edited: