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    cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverter

    Hello all,
    I am currently working on layout in cadence virtuoso having calibre tool. In inverter while doing DRC,I am getting the following error which I am unable to solve since 1 month and I didn't found in google.

    1. Offgrid error
    2. Orthogonal corners are not allowed at die edge.
    3. related to M1,M2,GC coverage. (GC coverage less than 0.2)
    4. Sized AA density
    5. M1 area less than 0.414

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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    This is probably a layout which you transferred from an other layout tool, the layout created with a different grid size. So you'd have to regrid it first to the grid size of your current technology file (may be 10nm for a 180nm technology). How this is done depends on the Virtuoso software version used, but should be accessible via a menu.



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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    No, I have created the layout and I am using 180nm technology. So I have used default major and minor spacing and X -snap and Y - snap Spacing of 0.001.
    I was getting 1000 offgrid errors then in main terminal I wrote "howFixOffGrid()" after that I am getting 10-15 offgrid errors. And for rest of the errors I am not getting anything how to remove them.



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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    So may be you didn't create rectangles, i.e. orthogonal edges only. Check that, and if so, repair it!



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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    I have created using rectangles and paths. This is the layout of inverter which I made.

    Click image for larger version. 

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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    Quote Originally Posted by ADI21 View Post
    I have created using rectangles and paths.
    Right, actually looks so. Now 2 suggestions:

    1. Check if your chosen grid size (0.001 without unit could mean 1nm or 1µm or 1mm) corresponds to your technology's grid size (see your technology file). Unit sizes depend on a scale parameter - if it exists.

    2. If the remaining offgrid error messages contain coordinates (or are backannotated to the corresponding points in the layout), check these points, and, if possible move them to the nearest grid points.



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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    Is technology file means DRC rule file? In rule file, 5nm is given which I used as a snap spacing.
    Ya it contains coordinates,I will try to move them to the nearest points but I don't know what is backannotated. Can you please explain about that.



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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    Quote Originally Posted by ADI21 View Post
    technology file means DRC rule file?
    No. There should be a special technology file (techFile) somewhere in your PDK's Virtuoso setUp, callable from one of the layout menus.

    Quote Originally Posted by ADI21 View Post
    ... I don't know what is backannotated.
    backannotated means back annotation of the reported error to the location with the coordinates of this error in the layout: there should be an error mark (on error dwg layer) which reports this error by clicking on it.



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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    Ya, by clicking on the error it highlights the portion in the layout where error is present and it also shows the coordinates.
    But for some of the errors it highlights the whole layout like - M1,M2,GC coverage error, offgrid error and I don't know what does coverage error means?



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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    Quote Originally Posted by ADI21 View Post
    But for some of the errors it highlights the whole layout like - M1,M2,GC coverage error, offgrid error and I don't know what does coverage error means?
    Coverage is the same as pattern density or density check, see dick_freebird's contribution in this parallel thread.

    Don't mind these coverage errors in your current design state, or switch off these checks before you start the DRC check, as suggested by Dick in the same thread.


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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    Quote Originally Posted by erikl View Post
    Coverage is the same as pattern density or density check, see dick_freebird's contribution in this parallel thread.

    Don't mind these coverage errors in your current design state, or switch off these checks before you start the DRC check, as suggested by Dick in the same thread.
    it is likely that there are two DRC decks, one for IP and one for CHIP level. the first one shouldn't have density checks.


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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    Ok. Thank you so much.

    - - - Updated - - -

    that means I can ignore the coverage error and min area error?
    Last edited by ADI21; 12th August 2016 at 13:26.



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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    You can probably ignore all the errors you listed until you get to some larger blocks. Some may not go away until you complete your layout.



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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    You would be best off to ignore the min area errors after
    determining that each of them will be fixed by attaching
    the block usefully. This is generally the case, but wants
    inspection. In some technologies a minimum via and its
    surround will violate min area and then someone using
    your cell will find their own min-area errors in your data
    levels if they try to drop down using a single stacked via.
    If it doesn't blow your layout area then consider redundant
    contacts / vias which tend to exceed min area naturally
    as well as incrementally improving yield / reliability. If
    you cared about such things in your present environment.



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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    Quote Originally Posted by rangermad View Post
    You can probably ignore all the errors you listed until you get to some larger blocks. Some may not go away until you complete your layout.
    I wouldn't ignore the min area errors. Those should be fixed at IP level.



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    Re: cadence virtuoso layout DRC errors using calibre tool in180nm technology- Inverte

    Larger blocks means opamp,ADC something like that? But in mostly every circuit inverter is used. If in inverter,all the errors are not removed then how come other complex layouts will be error free?

    - - - Updated - - -

    Which contacts are redundant? Wherever their is an intersection of M1,M2 or M1,GC or any other, contacts are needed?
    I have also noticed that if I am only using M1 not M2,then M1 are crossing(intersecting) each other but no error is displayed. Is it the right way?

    - - - Updated - - -

    Then how did you solved all this errors?



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