How to select nldmos for BUCK conveter

Hello ，

Does anybody know how to select nldmos for your BUCK converter based on BVDSS/eSOA /CHC ?

For example , if design a 17V BUCK converter , there will be 16V/18V/20V nldmos could be used ,and their Rsp and BVDSS are different ,so if I select 20V nldmos , it will be more robust for my design , but its Rsp will be larger so need more die size .In contrary , if I select 16V nldmos ,its Rsp is smaller ,and will save some die size ,but i am not sure if it's robust enough .

I know somebody also use 12V nldmos used as low side powerfet in their 16V/17V buck converter design , this depends on the process used , here I want to know how to evaluate if the performance of 12V nldmos is good enough for my design .For example , if the minimum BVDSS of 12V nldmos > 21V (17V+4V margin) , I could use it as low side fet in my 17V BUCK converter ? Here 4V margin is because of SW(PH) point will have 3V~4V ring during switching based on my experience .

Also eSOA/CHC characteristic will take an effect to your selection .

So does anybody could guide me on how to select your HS/LS nldmos or recommend some materials to me about this topic ?

Thanks so much .

If you ask a power supply designer, +20% design margin
on power switch voltage handling will get you only scorn.
If this is a school project then maybe nobody will notice.
Anyone whose reputation is on the hook for using your
product would insist on more confidence I expect. And a
die that nobody buys has pretty lousy manufacturing
economics no matter what kind of layout area hero you
think you're being.

What quality of input supply can you count on? Like,
"12V" automotive might say 17V for the upper end of
normal charging voltage, but what's left in the bag for
load dump or battery open circuit? Pick your conditions
and abnormal conditions based on end use and the
spec regime that your customers work to, which likely
includes faults / threats that an IC designer is unaware
of (unless steeped in application-niche lore).